PXIe-6593 16.3 Gbps High-Speed Serial Instrument
The PXIe-6593 is an 8-channel PXI high-speed serial instrument designed for validating, interfacing with and testing high-speed serial protocols. It combines FPGA-based protocol implementation, multigigabit serial transceivers and high-bandwidth PXI Express data streaming in a single programmable instrument.
The module supports data rates from 500 Mbps to 16.3 Gbps per lane across eight bidirectional TX/RX lanes. Its Xilinx Kintex UltraScale FPGA can be programmed with LabVIEW FPGA to implement standard or custom serial protocols for semiconductor testing, protocol validation, device interfacing and high-performance embedded systems.
With 4 GB of onboard DRAM, QSFP28 connectivity and a PCI Express Gen 3 x8 backplane interface, the PXIe-6593 is suitable for applications requiring deterministic FPGA processing and high-throughput data movement in a PXI test system.
Key Features of the PXIe-6593
- Eight bidirectional high-speed serial TX/RX lanes
- 500 Mbps to 16.3 Gbps data rate per lane
- Xilinx Kintex UltraScale KU040 or KU060 FPGA
- 4 GB onboard DRAM
- QSFP28 high-speed serial connectivity
- Copper and optical cabling options
- Eight auxiliary GPIO channels
- PCI Express Gen 3 x8 PXI backplane interface
- Up to 7 GB/s host streaming bandwidth
- Programmable with LabVIEW FPGA
- Supports standard and custom serial protocols
- Internal and external reference clock options
- PXI Express timing and synchronization support
- Suitable for protocol generation, acquisition and real-time processing
PXIe-6593 Technical Specifications
| Product Model | PXIe-6593 |
|---|---|
| Product Type | PXI High-Speed Serial Instrument |
| High-Speed Serial Channels | 8 bidirectional TX/RX lanes |
| Minimum Data Rate | 500 Mbps per lane |
| Maximum Data Rate | 16.3 Gbps per lane |
| FPGA Options | Xilinx Kintex UltraScale KU040 or KU060 |
| Onboard DRAM | 4 GB |
| Host Streaming Bandwidth | Up to 7 GB/s |
| PXI Backplane Interface | PCI Express Gen 3 x8 |
| High-Speed Connector | QSFP28 |
| Cabling Options | Copper or optical |
| Auxiliary Digital I/O | 8 GPIO channels |
| Programming Environment | LabVIEW FPGA |
| Operating Temperature | 0°C to 55°C |
| Required Slot Cooling Capacity | 58 W or greater |
| Form Factor | PXI Express |
PXIe-6593 Part Numbers and FPGA Options
| Part Number | FPGA | DRAM | Maximum Data Rate |
|---|---|---|---|
| 785976-01 | Kintex UltraScale KU040 | 4 GB | 16.3 Gbps per lane |
| 785977-01 | Kintex UltraScale KU060 | 4 GB | 16.3 Gbps per lane |
Both versions provide eight bidirectional serial lanes, 4 GB of DRAM and the same maximum lane rate. The primary difference is FPGA capacity. The KU060 version offers more FPGA logic, DSP resources and embedded block memory for larger or more complex protocol implementations.
FPGA-Based Serial Protocol Testing
The PXIe-6593 is built around a user-programmable FPGA instead of a fixed-function protocol engine. Engineers can configure the FPGA to generate, receive, decode, process and respond to high-speed serial data with hardware-timed performance.
This architecture is useful when a standard protocol analyzer does not provide the required timing behavior, lane configuration, data processing or application-specific interface. Protocol functions can be implemented directly in the FPGA, allowing the instrument to interact with a device under test in real time.
The FPGA can perform tasks such as:
- Serial data generation and acquisition
- Protocol encoding and decoding
- Packet and frame processing
- Error insertion and detection
- Custom triggering and event detection
- Real-time data filtering
- Lane alignment and synchronization
- Device emulation
- Protocol conversion and bridging
- Deterministic response generation
Eight Bidirectional TX/RX Lanes
The PXIe-6593 provides up to eight transmit and eight receive lanes through its FPGA multigigabit transceivers. Each lane supports serial data rates from 500 Mbps to 16.3 Gbps without the line-rate gap found on some earlier high-speed serial instruments.
The lanes can be configured independently or grouped into multilane links according to the selected protocol and FPGA design. This flexibility supports applications ranging from individual serial interfaces to x4 and x8 high-bandwidth connections.
QSFP28 Connectivity
The module uses QSFP28 connectivity for its high-speed serial lanes. Compatible passive copper and active optical cables can be selected according to transmission distance, signal-integrity requirements and the interface used by the device under test.
QSFP28 connectivity provides a compact method for routing multiple serial lanes. Application-specific breakout cables or interface fixtures may be required when connecting the PXIe-6593 to individual lanes, optical transceivers, semiconductor load boards or custom electronic hardware.
Onboard DRAM and Data Streaming
The PXIe-6593 includes 4 GB of onboard DRAM that can be accessed by the FPGA for waveform storage, packet buffering and high-speed data capture. The onboard memory helps maintain deterministic data movement when the serial link rate exceeds the immediate processing or transfer rate of the host system.
A PCI Express Gen 3 x8 backplane interface supports high-throughput streaming between the FPGA, PXI controller and other compatible PXI Express modules. Host streaming bandwidth can reach up to 7 GB/s under supported system configurations.
The module can also participate in peer-to-peer data transfers with compatible FPGA-enabled or high-throughput PXI instruments, reducing unnecessary transfers through the host processor.
Reference Clocking and Synchronization
High-speed serial applications require a stable, low-jitter reference clock. The PXIe-6593 includes an onboard synthesizer and supports importing or exporting reference clocks through its front-panel connections.
The module can also use supported PXI Express backplane clocks, including the 100 MHz PXI Express reference clock and compatible differential star clock resources. These options help synchronize the PXIe-6593 with digitizers, digital waveform instruments and other FPGA-based modules in a common test system.
Auxiliary Digital I/O
Eight auxiliary GPIO channels are available for lower-speed control, triggering, handshaking and device configuration. These channels can coordinate serial data operation with external fixtures, device reset lines, status signals or test-system control circuitry.
The auxiliary GPIO should not be confused with the eight multigigabit serial lanes. GPIO channels are intended for general digital control, while the FPGA transceiver lanes handle high-speed differential serial communication.
Supported Protocol Applications
The programmable FPGA architecture allows the PXIe-6593 to be used with multiple standard and custom serial protocols. Protocol implementation depends on the selected FPGA personality, IP, reference project and application software.
Protocol applications associated with the PXIe-6593 include:
- Xilinx Aurora 64b/66b
- Xilinx Aurora 8b/10b
- Gigabit Ethernet
- JESD204B and JESD204C
- Fibre Channel
- ARINC 818
- Serial RapidIO
- Serial Front Panel Data Port
- Proprietary FPGA-to-FPGA links
- Custom semiconductor serial interfaces
Protocol compatibility does not necessarily mean that every implementation is supplied as a ready-to-run application. Some protocols require custom FPGA development, third-party IP or adaptation of an available reference design.
Typical PXIe-6593 Applications
- High-speed serial protocol validation
- Semiconductor functional and production testing
- JESD204B and JESD204C interface testing
- FPGA and ASIC interface validation
- Protocol generation and acquisition
- Custom device interfacing
- High-speed data streaming
- Error insertion and receiver testing
- Hardware protocol emulation
- Aerospace video interface testing
- Embedded system validation
- Research and communication system development
Software and FPGA Development
The PXIe-6593 is programmed using LabVIEW FPGA and supported NI high-speed serial instrument software. Host applications communicate with the FPGA through NI-RIO interfaces, while FPGA code controls the serial transceivers, DRAM, clocks and auxiliary digital I/O.
Available example projects and instrument design libraries can shorten development time for selected applications. Engineers can modify existing personalities, integrate supported FPGA IP or create custom protocol logic based on system requirements.
Before purchasing, verify the required LabVIEW, LabVIEW FPGA, FlexRIO or Instrument Design Libraries software versions. FPGA compilation tools and applicable licenses may need to be ordered or installed separately.
PXIe-6593 Chassis Requirements
The PXIe-6593 requires a PXI Express chassis with an available compatible peripheral slot and sufficient backplane bandwidth. The selected slot should provide a PCI Express Gen 3 x8 link when maximum host streaming performance is required.
The module also requires a chassis slot cooling capacity of at least 58 W. Not every PXI Express chassis or slot provides the required cooling performance, so chassis specifications must be checked before installation.
For multi-instrument streaming systems, also verify the chassis PCI Express topology, controller bandwidth and available data paths between the PXIe-6593 and other modules.
PXIe-6593 Troubleshooting
The Serial Link Does Not Establish
Verify that the FPGA personality supports the intended protocol, encoding method, reference clock and lane rate. Check that both ends of the link use compatible transceiver settings and lane assignments.
Bit Errors Occur at Higher Data Rates
Inspect the QSFP28 cable, breakout assembly, connectors and device-under-test interface. Excessive cable length, poor impedance control, incorrect equalization or an unstable reference clock can reduce signal integrity.
The Module Is Not Detected
Confirm that the PXIe-6593 is installed in a compatible PXI Express peripheral slot. Check the PXI controller, required NI software and module recognition in NI Measurement & Automation Explorer.
Streaming Performance Is Lower Than Expected
Check the chassis backplane topology, controller interface, storage performance and PCI Express link width. Maximum streaming performance requires a complete system capable of sustaining the requested data rate.
The FPGA Design Does Not Fit
Review FPGA logic, memory and DSP utilization. Applications that exceed the KU040 resources may require the KU060 version or a higher-capacity high-speed serial instrument.
The Module Temperature Is Too High
Verify that the chassis provides at least 58 W of slot cooling capacity. Keep air vents clear and confirm that the chassis fan mode is appropriate for high-power PXI Express modules.
PXIe-6593 Compared with Similar High-Speed Serial Instruments
| Model | Serial Lanes | Maximum Lane Rate | FPGA | DRAM | Connector |
|---|---|---|---|---|---|
| PXIe-6591 | 8 TX/RX | 12.5 Gbps | Kintex-7 K410T | 2 GB | Mini-SAS HD |
| PXIe-6592 | 4 TX/RX | 10.3125 Gbps | Kintex-7 K410T | 2 GB | SFP+ |
| PXIe-6593 | 8 TX/RX | 16.3 Gbps | Kintex UltraScale KU040 or KU060 | 4 GB | QSFP28 |
| PXIe-6594 | 8 TX/RX | 28.2 Gbps | Kintex UltraScale+ KU15P | 8 GB | QSFP28 |
| PXIe-7903 | 48 TX/RX | 28.2 Gbps | Virtex UltraScale+ XCVU11P | 20 GB | Mini-SAS HD |
The PXIe-6593 provides a balance between serial lane count, maximum data rate, FPGA capacity and QSFP28 connectivity. The PXIe-6594 is more suitable when lane rates above 16.3 Gbps are required, while the PXIe-7903 targets applications needing substantially more serial lanes and FPGA resources.
Recommended Related Products
- PXIe-6594 High-Speed Serial Instrument – Provides eight TX/RX lanes with data rates up to 28.2 Gbps and a larger UltraScale+ FPGA.
- PXIe-6592 High-Speed Serial Instrument – A four-lane SFP+ instrument for applications requiring data rates up to 10.3125 Gbps.
- PXIe-6591 High-Speed Serial Instrument – Offers eight Mini-SAS HD serial lanes with a Kintex-7 FPGA.
- PXIe-7902 High-Speed Serial Module – Provides 24 TX/RX lanes for higher-density serial interface applications.
- PXIe-7903 High-Speed Serial Module – Provides 48 TX/RX lanes, up to 28.2 Gbps per lane and extensive FPGA resources.
How to Select the Correct PXIe-6593
Choose between the KU040 and KU060 versions according to the FPGA resources required by the protocol implementation. The KU040 version is suitable for less complex designs, while the KU060 version provides additional logic cells, DSP slices and embedded memory for larger FPGA personalities.
Before ordering, confirm the following:
- Required serial protocol and FPGA personality
- Number of TX and RX lanes
- Minimum and maximum lane rates
- KU040 or KU060 FPGA capacity
- QSFP28 copper or optical cabling
- Breakout cable and fixture requirements
- PXI Express chassis cooling capacity
- Backplane PCI Express link width
- Controller and storage streaming bandwidth
- LabVIEW FPGA and driver compatibility
Why Choose the PXIe-6593?
The PXIe-6593 combines eight multigigabit serial transceivers, a programmable Kintex UltraScale FPGA, 4 GB of DRAM and high-throughput PXI Express streaming. It allows engineers to create application-specific serial instruments instead of being limited to the functionality of a fixed protocol tester.
Its FPGA-based architecture is especially valuable for custom protocols, deterministic device interaction, semiconductor testing and test systems that must evolve as interface requirements change.
Frequently Asked Questions
What is the PXIe-6593?
The PXIe-6593 is an eight-lane PXI high-speed serial instrument used to generate, acquire and process serial data through a programmable FPGA.
What is the maximum data rate of the PXIe-6593?
Each high-speed serial lane supports a maximum data rate of 16.3 Gbps.
How many serial channels does the PXIe-6593 provide?
The module provides eight bidirectional lanes, with up to eight transmit and eight receive channels.
What is the difference between 785976-01 and 785977-01?
Part number 785976-01 uses a Kintex UltraScale KU040 FPGA, while 785977-01 uses the larger KU060 FPGA. Both versions provide eight lanes, 4 GB of DRAM and maximum data rates of 16.3 Gbps per lane.
Does the PXIe-6593 include a fixed protocol analyzer?
No. It is an FPGA-based instrument whose protocol behavior is determined by the loaded FPGA personality. Available examples can be used for selected protocols, while other applications may require custom development.
Can the PXIe-6593 test JESD204 interfaces?
Yes, the hardware can be used for JESD204B and JESD204C applications when configured with suitable FPGA IP, clocking and application software.
What connector does the PXIe-6593 use?
The high-speed serial interface uses QSFP28 connectivity and supports compatible copper or optical cable solutions.
How much onboard memory does it have?
Both PXIe-6593 versions include 4 GB of onboard DRAM for high-speed buffering, waveform storage and FPGA data processing.
What chassis does the PXIe-6593 require?
It requires a compatible PXI Express chassis with an appropriate peripheral slot, sufficient PCI Express bandwidth and at least 58 W of slot cooling capacity.
Can the PXIe-6593 be programmed with LabVIEW FPGA?
Yes. LabVIEW FPGA can be used to customize protocol logic, data processing, triggering, memory access and device interaction.
Request a Quote for the PXIe-6593
Contact us for current availability, lead time and project pricing for the PXIe-6593 High-Speed Serial Instrument. Please specify whether you require part number 785976-01 with the KU040 FPGA or 785977-01 with the KU060 FPGA.
We can also help verify compatible PXI Express chassis, controllers, QSFP28 cables and related high-speed serial modules for your test system.
