PXIe-6592 4-Channel 10.3125 Gbps High-Speed Serial Instrument
The NI PXIe-6592, also documented as the PXIe-6592R, is an FPGA-based PXI Express high-speed serial instrument designed for SerDes validation, protocol testing and custom high-speed digital interfacing. It provides four bidirectional TX/RX serial lanes, with each lane supporting rates up to 10.3125 Gbit/s.
The PXIe-6592 combines four front-panel SFP+ ports with a user-programmable Xilinx Kintex-7 XC7K410T FPGA. Engineers can implement standards-based or proprietary serial protocols, perform real-time error checking and process received data directly in FPGA hardware.
The module also includes 2 GB of onboard DRAM, four auxiliary digital I/O lines and a PCI Express Gen 2 x8 interface supporting high-speed data movement between the FPGA, host controller and other PXI instruments.
PXIe-6592 Product Overview
The PXIe-6592 is designed for engineers who require more flexibility than a fixed-function serial analyzer. Its FPGA architecture allows application-specific protocol logic, packet processing, triggering, error detection and data reduction to be implemented directly in hardware.
Each of the four SFP+ ports connects to one FPGA multigigabit transceiver lane. All four ports can operate simultaneously when the FPGA design, clock configuration, power budget and application architecture support the required operation.
The standard NI part number is 783639-01. NI currently classifies the PXIe-6592 as a mature product and identifies the PXIe-6593 KU060 version, part number 785977-01, as a recommended replacement for new designs.
Key Features of the PXIe-6592
Four Bidirectional Serial Lanes
The PXIe-6592 provides four TX/RX high-speed serial lanes. Each lane is routed to a dedicated SFP+ connector, allowing independent point-to-point serial links to be implemented.
Up to 10.3125 Gbit/s Per Channel
Each lane supports line rates from 500 Mbit/s to 8 Gbit/s and from 9.8 Gbit/s to 10.3125 Gbit/s. There is an unsupported rate gap between 8 Gbit/s and 9.8 Gbit/s.
Four SFP+ Ports
The module provides four SFP+ cages identified as Port 0 through Port 3. Compatible SFP+ direct-attach copper cables and optical transceivers can be used according to the application.
Standard SFP modules are not supported, even though they may fit mechanically into an SFP+ cage. Use compatible SFP+ cables and transceivers specified for the PXIe-6592.
Xilinx Kintex-7 FPGA
The PXIe-6592 includes a Xilinx Kintex-7 XC7K410T FPGA. Its logic, DSP and embedded-memory resources support protocol state machines, packet parsing, error detection, triggering and real-time data processing.
2 GB Onboard DRAM
The onboard 2 GB DRAM bank can store captured packets, generated data, replay sequences and intermediate FPGA processing results. The memory has a theoretical maximum internal bandwidth of 10.5 GB/s.
Four Auxiliary Digital I/O Lines
Four front-panel PFI connections can be used for digital communication, triggers and clock routing. These lines support custom synchronization between the PXIe-6592 and external hardware.
High-Speed Host Streaming
The PCI Express Gen 2 x8 interface supports host and peer-to-peer streaming bandwidth up to approximately 3.2 GB/s under suitable system conditions.
Custom Protocol Implementation
The user-programmable FPGA can implement standard or proprietary high-speed serial protocols using LabVIEW FPGA, compatible reference designs, Socketed CLIP and imported HDL or protocol IP.
Real-Time FPGA Processing
Received serial data can be decoded, filtered, compared or modified directly in the FPGA. Processing data before transferring it to the host helps reduce latency and host-controller bandwidth requirements.
PXI Timing and Synchronization
The PXIe-6592 can use front-panel clock resources, PXIe_CLK100 and differential star timing from the PXI Express backplane. These resources support synchronization with other PXI modules.
PXIe-6592 Technical Specifications
| Product Model | NI PXIe-6592 / PXIe-6592R |
|---|---|
| Part Number | 783639-01 |
| Product Type | FPGA-Based High-Speed Serial Instrument |
| Bidirectional Serial Channels | 4 TX/RX lanes |
| Maximum Line Rate | 10.3125 Gbit/s per channel |
| Supported Line-Rate Ranges | 500 Mbit/s to 8 Gbit/s and 9.8 Gbit/s to 10.3125 Gbit/s |
| High-Speed Serial Connectors | 4 × SFP+ |
| Cabling Options | SFP+ copper or optical |
| Auxiliary Digital I/O | 4 single-ended PFI lines |
| PFI Connectors | 4 × SMB |
| FPGA | Xilinx Kintex-7 XC7K410T |
| FPGA Package | FFG900 |
| FPGA Speed Grade | -2 |
| FPGA LUTs | 254,200 |
| FPGA Flip-Flops | 508,400 |
| DSP48 Slices | 1,540 |
| Embedded Block RAM | 28,620 kbit |
| Onboard DRAM | 2 GB, single bank |
| DRAM Interface | 512-bit at 166 MHz |
| DRAM Theoretical Bandwidth | 10.5 GB/s |
| PXI Express Interface | PCI Express Gen 2 x8 |
| Host and P2P Streaming | Up to approximately 3.2 GB/s |
| Data Transfer Methods | DMA, interrupts and programmed I/O |
| DMA Interrupt Channels | 32 |
| Transceiver Reference Clock Range | 60 MHz to 700 MHz |
| Maximum Backplane Power | 38.25 W |
| Operating Temperature | 0°C to 45°C |
| Software | LabVIEW FPGA Module and High-Speed Serial Instrument support |
| Lifecycle Status | Mature |
Understanding the Four-Port Architecture
The PXIe-6592 provides four independent SFP+ ports. Each port contains one transmit lane and one receive lane connected directly to the Kintex-7 FPGA multigigabit transceiver resources.
- Port 0: 1 TX/RX lane
- Port 1: 1 TX/RX lane
- Port 2: 1 TX/RX lane
- Port 3: 1 TX/RX lane
At 10.3125 Gbit/s per lane, the four ports provide more than 41 Gbit/s of combined raw line-rate capacity in each direction. Actual user-data throughput is lower because of protocol encoding, packet overhead and implementation requirements.
How the PXIe-6592 Works
Incoming serial data enters through an SFP+ cable or optical transceiver and reaches the Kintex-7 multigigabit transceiver. The transceiver performs serial-to-parallel conversion and clock recovery before passing the data into the FPGA fabric.
The FPGA can then perform functions such as:
- Line encoding and decoding
- Frame and packet detection
- Protocol state-machine control
- Error detection and counting
- Packet filtering and classification
- Trigger generation
- Data buffering in onboard DRAM
- Packet modification and retransmission
Processed results can be stored in DRAM, transferred to the host through DMA or transmitted through another SFP+ port.
Kintex-7 FPGA Resources
The Kintex-7 XC7K410T provides 254,200 lookup tables, 508,400 flip-flops, 1,540 DSP48 slices and approximately 28.6 Mbit of embedded block RAM.
These resources support multiple serial links together with custom protocol and signal-processing logic. FPGA block RAM can be used for short buffers and lookup tables, while DSP slices support mathematical and filtering operations.
Large FPGA designs must be evaluated for logic utilization, clock-domain crossings, routing congestion, transceiver placement and timing closure.
Onboard DRAM
The PXIe-6592 includes 2 GB of onboard DRAM connected directly to the FPGA. It provides substantially more storage than the FPGA’s embedded block RAM.
Typical uses include:
- Serial packet capture
- Generated traffic storage
- Packet replay
- Large lookup tables
- Temporary data buffering
- Rate matching between serial links and the host
The 512-bit DRAM interface operates at 166 MHz and has a theoretical maximum bandwidth of 10.5 GB/s. Practical performance depends on the FPGA memory-controller implementation and data-access pattern.
Host and Peer-to-Peer Streaming
The PCI Express Gen 2 x8 interface supports high-speed transfers between the FPGA and PXI controller. Host-streaming bandwidth can reach approximately 3.2 GB/s under suitable system conditions.
Peer-to-peer streaming can move data directly between compatible PXI Express modules without routing every transfer through host memory. For example, serial data can be transferred to a digitizer, FPGA module or storage-oriented module within the same PXI system.
The combined serial line capacity can exceed the host interface bandwidth. FPGA filtering and data reduction may therefore be required when several ports operate at high rates simultaneously.
SFP+ Connectivity
The PXIe-6592 accepts compatible SFP+ copper cables and optical transceivers. Connection choices depend on distance, required electrical isolation and the target interface.
SFP+ Direct-Attach Copper
Direct-attach copper cables are suitable for short rack and laboratory connections. They provide a simple point-to-point connection without separate optical transceivers.
SFP+ Optical Transceivers
Compatible SFP+ optical transceivers and fiber cables can support longer distances and reduce electrical coupling between systems.
SFP Compatibility Limitation
Although SFP and SFP+ modules have similar mechanical dimensions, standard SFP transceivers are not supported by the PXIe-6592. Use SFP+ components verified for the module and required line rate.
Auxiliary Digital I/O and PFI Connections
The PXIe-6592 provides four SMB PFI connectors:
- PFI 0 / CLK IN / CLK OUT
- PFI 1 / CLK OUT
- PFI 2 / CLK OUT
- PFI 3 / CLK OUT
These lines can be used for external triggers, low-speed digital communication and clock routing. The auxiliary digital lines can support clock rates up to 50 MHz or data rates up to 100 Mbit/s, depending on the FPGA implementation.
Clocking and Synchronization
Stable reference clocking is essential for multigigabit serial operation. The PXIe-6592 can use:
- PFI 0 / CLK IN front-panel clock input
- PXIe_CLK100 backplane reference
- PXIe_DStarA differential star clock
- Internal onboard clock resources
The multigigabit transceiver reference-clock system supports frequencies from approximately 60 MHz to 700 MHz. All clock sources and output frequencies must be compatible with the selected FPGA transceiver configuration and serial protocol.
Custom Serial Protocol Implementation
The PXIe-6592 does not operate as a universal fixed-protocol tester without an appropriate FPGA personality. Engineers can use reference designs, compatible protocol IP or custom HDL to implement the required communication interface.
Possible FPGA functions include:
- 8b/10b and 64b/66b encoding
- Link training and synchronization
- Packet framing and deframing
- CRC generation and checking
- Error injection
- Packet sequence verification
- Loopback and retransmission
- Custom control and status registers
Reference designs have been available for applications such as Gigabit Ethernet, 10 Gigabit Ethernet and Xilinx Aurora. Verify software-version and hardware compatibility before beginning development.
Typical PXIe-6592 Applications
- SerDes interface validation
- 10 Gigabit Ethernet development
- High-speed serial protocol testing
- Custom protocol implementation
- Optical and copper link testing
- FPGA and ASIC validation
- Bit-error and link-integrity testing
- Packet generation and analysis
- Data recording and replay
- Real-time packet processing
- Semiconductor functional testing
- High-performance embedded systems
- Automated production testing
- Aerospace and defense communication testing
SerDes and Semiconductor Validation
The PXIe-6592 can generate and receive high-speed serial traffic for validating FPGA, ASIC and communication-device interfaces. Custom logic can perform link initialization, error injection, response validation and real-time error counting.
When combined with PXI oscilloscopes, source measure units and power supplies, the module can help characterize serial-link behavior across supply voltage, timing and operating conditions.
PXIe-6592 Software Support
The PXIe-6592 is programmed using the LabVIEW FPGA Module and NI support for high-speed serial instruments. Host applications can configure the FPGA, control tests and transfer measurement data.
Development resources may include:
- LabVIEW FPGA Module
- LabVIEW Instrument Design Libraries for High-Speed Serial Instruments
- Socketed Component-Level IP
- High-throughput LabVIEW FPGA designs
- Compatible Xilinx protocol IP
- VHDL integration
- LabVIEW and ANSI C host APIs
Developing a new serial protocol requires experience with FPGA architecture, clock-domain management, digital logic and high-speed serial transceivers.
PXIe-6592 System Requirements
A complete PXIe-6592 system normally requires:
- A compatible PXI Express chassis
- An embedded PXI controller or external computer interface
- A PXI Express slot with adequate link width and cooling
- LabVIEW and the LabVIEW FPGA Module
- NI High-Speed Serial Instrument support software
- Compatible FPGA compilation tools
- SFP+ direct-attach cables or optical transceivers
- Appropriate protocol IP or custom FPGA logic
The module supports x1, x4, x8 and x16 PXI Express or hybrid-compatible slots, but practical host bandwidth depends on the slot’s PCI Express link width.
Cooling and Installation Considerations
The PXIe-6592 can consume up to 38.25 W from the PXI Express backplane, depending on FPGA logic and transceiver utilization. Adequate chassis airflow is essential for reliable operation.
Recommended installation practices include:
- Use a chassis with sufficient cooling capacity
- Set the chassis fan mode according to the module requirements
- Install filler panels in unused slots
- Keep chassis air inlets and outlets unobstructed
- Monitor FPGA power and thermal utilization
PXIe-6592 vs PXIe-6591R
| Specification | PXIe-6591R | PXIe-6592 |
|---|---|---|
| TX/RX Lanes | 8 | 4 |
| Maximum Line Rate | 12.5 Gbit/s | 10.3125 Gbit/s |
| Connector Type | Mini-SAS HD | SFP+ |
| FPGA | Kintex-7 XC7K410T | Kintex-7 XC7K410T |
| Onboard DRAM | 2 GB | 2 GB |
| Auxiliary Digital I/O | 20 single-ended lines | 4 single-ended lines |
| Primary Difference | More lanes and Mini-SAS HD connectivity | Individual SFP+ interfaces |
The PXIe-6591R is preferable when the application requires eight lanes or Mini-SAS HD connectivity. The PXIe-6592 is better suited to four independent SFP+ copper or optical links.
PXIe-6592 vs PXIe-6593
| Specification | PXIe-6592 | PXIe-6593 |
|---|---|---|
| TX/RX Lanes | 4 | 8 |
| Maximum Line Rate | 10.3125 Gbit/s | 16.3 Gbit/s |
| FPGA | Kintex-7 K410T | Kintex UltraScale KU040 or KU060 |
| Onboard DRAM | 2 GB | 4 GB |
| Host Streaming Bandwidth | Approximately 3.2 GB/s | Up to approximately 7 GB/s |
| Connector Type | SFP+ | QSFP28 |
| Lifecycle Position | Mature | Recommended newer platform |
The PXIe-6593 provides more lanes, a higher line rate, additional memory and greater host bandwidth. However, migrating an existing PXIe-6592 system may require changes to FPGA code, connectors, cables and fixtures.
Comparison with Related High-Speed Serial Instruments
| Model | TX/RX Lanes | Maximum Line Rate | FPGA | Connector |
|---|---|---|---|---|
| PXIe-6591R | 8 | 12.5 Gbit/s | Kintex-7 K410T | Mini-SAS HD |
| PXIe-6592 | 4 | 10.3125 Gbit/s | Kintex-7 K410T | SFP+ |
| PXIe-6593 | 8 | 16.3 Gbit/s | Kintex UltraScale | QSFP28 |
| PXIe-6594 | 8 | 28.2 Gbit/s | Kintex UltraScale+ | QSFP28 |
| PXIe-7902 | 24 | 12.5 Gbit/s | Virtex-7 485T | Mini-SAS HD |
| PXIe-7903 | 48 | 28.2 Gbit/s | Virtex UltraScale+ | Mini-SAS HD |
Recommended Related Products
- PXIe-6593 – recommended newer platform with eight lanes, up to 16.3 Gbit/s and a Kintex UltraScale FPGA.
- PXIe-6591R – eight-lane Kintex-7 serial instrument with Mini-SAS HD connectivity.
- PXIe-6594 – eight-lane, 28.2 Gbit/s serial instrument with a Kintex UltraScale+ FPGA.
- PXIe-7902 – 24-lane, 12.5 Gbit/s Virtex-7 serial instrument for higher channel density.
- PXIe-7903 – 48-lane, 28.2 Gbit/s serial instrument for high-density FPGA coprocessing.
- PXIe-1085 – high-bandwidth PXI Express chassis for FPGA and serial test systems.
- PXIe-8880 – embedded PXI controller for high-performance automated testing.
PXIe-6592 Selection Guidance
Before selecting the PXIe-6592, confirm that:
- No more than four TX/RX serial links are required
- The required line rate is within the supported ranges
- The application requires SFP+ connectivity
- Compatible SFP+ cables or optical transceivers are available
- The Kintex-7 FPGA provides sufficient logic and DSP resources
- 2 GB of onboard DRAM is sufficient
- The host-streaming requirement fits within the practical PXI bandwidth
- Suitable FPGA IP and development resources are available
- The mature product lifecycle is acceptable for the project
Common Troubleshooting Checks
The PXIe-6592 Is Not Detected
Confirm that the module is fully installed in a compatible PXI Express slot and that the required NI high-speed serial support software is installed. Use NI MAX to verify hardware recognition.
The SFP+ Link Does Not Establish
Confirm that the transceiver or cable is SFP+ rather than standard SFP. Verify the line rate, reference clock, encoding, link-training sequence and far-end device configuration.
All Four Ports Do Not Operate
Review the FPGA personality and confirm that logic has been implemented for every required port. Some sample projects use fewer than four ports even though the hardware supports simultaneous access to all four.
Bit Errors Occur at High Line Rates
Inspect the SFP+ cable or optical components, reference-clock jitter and receiver configuration. Confirm that the transceiver settings and signal-integrity requirements match the target link.
Host Streaming Cannot Sustain the Serial Data
Compare the combined serial payload with the practical host bandwidth. Use FPGA filtering, packet selection or data reduction to reduce the volume transferred to the controller.
The FPGA Compilation Fails
Check FPGA resource utilization, timing constraints, clock-domain crossings, transceiver placement, CLIP settings and software-tool compatibility.
Frequently Asked Questions
Is the official model PXIe-6592 or PXIe-6592R?
NI currently markets the product as PXIe-6592, while technical specifications and some documentation identify it as PXIe-6592R. Both names refer to the same reconfigurable high-speed serial instrument.
What is the PXIe-6592 used for?
It is used for SerDes validation, SFP+ link testing, custom serial protocols, FPGA processing and automated high-speed digital testing.
How many high-speed serial channels are available?
The module provides four bidirectional TX/RX channels, with one channel connected to each SFP+ port.
What is the maximum line rate?
The maximum line rate is 10.3125 Gbit/s per channel.
Which line rates are supported?
The supported ranges are 500 Mbit/s to 8 Gbit/s and 9.8 Gbit/s to 10.3125 Gbit/s.
Can standard SFP modules be used?
No. The PXIe-6592 supports SFP+ cables and transceivers, not standard SFP modules.
Can all four SFP+ ports operate simultaneously?
Yes. The hardware supports simultaneous use of all four ports when the FPGA application implements and configures them.
Which FPGA does the PXIe-6592 use?
It uses a Xilinx Kintex-7 XC7K410T FPGA.
How much onboard memory is available?
The PXIe-6592 includes 2 GB of onboard DRAM.
What is the PXIe-6592 part number?
The standard NI part number is 783639-01.
Which software is required?
Development typically requires LabVIEW, the LabVIEW FPGA Module and NI software support for high-speed serial instruments.
Is the PXIe-6592 recommended for new designs?
NI currently classifies it as a mature product. New systems should also evaluate the PXIe-6593, while existing systems may require the PXIe-6592 to preserve validated code and SFP+ connectivity.
Why Choose the PXIe-6592?
The PXIe-6592 is a practical option for systems requiring four independently accessible SFP+ serial links and a user-programmable FPGA. It combines 10.3125 Gbit/s operation, 2 GB DRAM, auxiliary digital I/O and high-speed PXI Express data transfer.
For existing installations, a replacement PXIe-6592 can help maintain validated FPGA code, SFP+ cabling and test fixtures without redesigning the system around a newer connector architecture.
Request a Quote for the PXIe-6592
Contact us for current availability, lead time and project pricing for the NI PXIe-6592 High-Speed Serial Instrument, part number 783639-01.
We can also help identify compatible SFP+ cables, optical transceivers, PXI Express chassis, controllers and replacement high-speed serial instruments for your application.
