PXIe-6536 32-Channel 25 MHz High-Speed Digital I/O Module
The NI PXIe-6536 is a high-speed digital I/O module designed for continuous data streaming, pattern generation, digital acquisition, change detection and custom protocol emulation. It provides 32 bidirectional single-ended digital channels, a maximum sample clock rate of 25 MHz and an aggregate streaming bandwidth of up to 100 MB/s.
The PXIe-6536 supports selectable 2.5 V, 3.3 V and 5 V TTL-compatible logic levels. Each digital channel has independent direction control, allowing engineers to combine input and output signals within the same test configuration.
Its PXI Express interface supports continuous DMA data transfer between the module and the host controller, making the PXIe-6536 suitable for image sensor testing, display-panel testing, pattern I/O and other data-intensive digital applications.
PXIe-6536 Product Overview
The PXIe-6536 is part of the NI high-speed digital I/O family. Unlike digital waveform instruments focused on deep onboard pattern memory, the PXIe-6536 is optimized for continuous streaming through the PXI Express bus.
The module can generate or acquire 32-bit digital words at up to 25 million samples per second. When all 32 channels are used, this corresponds to an aggregate data throughput of up to 100 MB/s.
Engineers can configure the digital direction on a per-channel basis, select an appropriate logic family and use internal or external sample clocks. The module also supports change detection, handshake operation, pattern matching, triggering and externally clocked digital transfers.
The standard NI part number for the PXIe-6536 is 779988-01.
Key Features of the PXIe-6536
32 Bidirectional Digital I/O Channels
The PXIe-6536 provides 32 single-ended digital channels. Each channel can be independently configured as an input or output, allowing a test application to combine data, command, status and control signals.
The channels can be used as a 32-bit parallel bus or divided into smaller groups for 8-bit, 16-bit and custom-width digital interfaces.
25 MHz Maximum Sample Clock
The internal sample clock operates from approximately 48 Hz to 25 MHz. External sample clocks can also be imported for applications that must synchronize digital transfers with a DUT-provided clock.
Up to 100 MB/s Aggregate Streaming
With 32 channels sampled at 25 MHz, the PXIe-6536 supports an aggregate transfer rate of up to 100 MB/s. The PXI Express interface allows generated and acquired data to be streamed continuously between the module and host memory.
Actual sustained performance depends on the chassis, controller, system bandwidth, software configuration and other modules sharing the PXI Express bus.
Selectable Logic Levels
The PXIe-6536 supports 2.5 V, 3.3 V and 5 V TTL-compatible logic families. The 5 V TTL-compatible setting uses 3.3 V output levels while providing thresholds compatible with 5 V TTL signals.
Per-Channel Direction Control
Every digital data channel can be independently configured as an input or output. This provides greater flexibility than devices that require the direction to be assigned to an entire 8-bit or 16-bit port.
Continuous DMA Streaming
The PXIe-6536 uses DMA transfers to move data between the module and system memory. This architecture supports continuous generation and acquisition without relying exclusively on deep onboard waveform storage.
Pattern Generation and Acquisition
The module can output predefined digital patterns and acquire DUT responses using hardware-timed sample clocks. Pattern I/O is useful for device initialization, parallel communication, digital sensor testing and automated functional validation.
Change Detection
Change-detection timing allows the module to acquire data when selected digital lines change state. This reduces unnecessary sampling when the application only needs to capture transitions or asynchronous events.
Handshake and Burst Handshake Modes
Handshake timing coordinates digital transfers with external ready and acknowledge signals. This is useful when the DUT cannot accept or provide data at a continuous fixed clock rate.
PXI Trigger and Clock Routing
The PXIe-6536 can route clocks, triggers and events through front-panel PFI channels and the PXI Express backplane. These resources support synchronization with other PXI modules.
PXIe-6536 Technical Specifications
| Product Model | NI PXIe-6536 |
|---|---|
| Part Number | 779988-01 |
| Product Type | High-Speed Digital I/O Module |
| Bus and Form Factor | PXI Express, single-slot 3U module |
| Digital I/O Channels | 32 bidirectional channels |
| Direction Control | Per channel |
| Signaling Type | Single-ended |
| Maximum Sample Clock | 25 MHz |
| Maximum Per-Channel Data Rate | 25 Mbit/s |
| Maximum Aggregate Streaming Rate | 100 MB/s with 32-bit data |
| Supported Logic Families | 2.5 V, 3.3 V and 5 V TTL compatible |
| Digital Input Range | -1 V to 6 V |
| Output Voltage Range | 0 V to 5 V operating compatibility |
| Output Impedance | 50 Ω nominal |
| Input Impedance | 50 kΩ nominal |
| Maximum Drive Strength | ±16 mA at 2.5 V; ±32 mA at 3.3 V |
| PFI Channels | 6 bidirectional PFI channels |
| External Clock Inputs | 2 front-panel clock-capable inputs |
| Internal Timebase | 200 MHz |
| Onboard FIFO | 2,048 samples |
| Transfer Methods | DMA and programmed I/O |
| Front Connector | 1 × VHDCI |
| Driver | NI-DAQmx |
| Module Width | 1 PXI Express slot |
Understanding the 100 MB/s Data Rate
The PXIe-6536 specification combines a 25 MHz sample clock with a 32-bit-wide digital port. Each complete sample contains four bytes:
25,000,000 samples/s × 4 bytes/sample = 100 MB/s
Therefore, 100 MB/s represents the maximum aggregate bandwidth when all 32 channels are transferred together. The corresponding rate on each individual digital channel is 25 Mbit/s.
This distinction is important when comparing the PXIe-6536 with digital waveform instruments that specify their maximum data rate on a per-channel basis.
How the PXIe-6536 Works
During digital generation, the host application fills a memory buffer with digital pattern data. NI-DAQmx transfers the data through the PXI Express bus into the module’s FIFO, and the PXIe-6536 outputs each sample using the selected sample clock.
During acquisition, the module samples the digital input lines and stores data temporarily in its FIFO. DMA then transfers the data continuously to system memory for analysis, storage or protocol decoding.
The onboard FIFO absorbs short variations in bus and software timing, while the PXI Express connection provides the sustained bandwidth required for continuous operation.
Digital Timing Modes
Sample Clock Timing
Sample clock timing generates or acquires one digital sample for every active clock edge. The clock can originate from the onboard timing engine, a PFI terminal or supported PXI Express backplane resources.
Pipelined Sample Clock
Pipelined timing provides additional timing flexibility between the clock and digital data. It can help meet interface setup-and-hold requirements when communicating with external hardware.
Burst Handshake
Burst handshake timing coordinates blocks of digital data with external flow-control signals. It is useful when a device transfers groups of samples but cannot sustain a continuous fixed-rate stream.
Handshake Timing
Handshake mode uses external request and acknowledge signals to control each transfer. This allows communication with devices whose response time varies from one sample to the next.
Change Detection
Change-detection acquisition captures the digital state when selected channels transition. Channels can be configured to respond to rising edges, falling edges or both edge directions.
On-Demand Digital I/O
Software-timed operation can be used when deterministic hardware timing is not required. The application reads or writes the digital state directly through NI-DAQmx calls.
Clock and Trigger Sources
The PXIe-6536 supports several clock and trigger resources, including:
- Internal 200 MHz timebase
- Internally divided sample clock
- PFI 4 and PFI 5 sample clock terminals
- PFI 0 through PFI 5 timing and trigger terminals
- PXI trigger bus resources
- PXI_STAR timing resource
- PXIe differential star trigger resources
- Pattern-match acquisition triggers
Available routing depends on the selected timing mode and whether the operation is configured for generation or acquisition.
Continuous Digital Data Streaming
The PXIe-6536 is designed for applications where digital data must be continuously generated or acquired. Instead of requiring the complete waveform to fit inside onboard memory, data can be transferred between the module and host memory during operation.
Continuous streaming is particularly useful for:
- Long or nonrepeating digital patterns
- Extended image sensor captures
- Display-panel stimulus generation
- Continuous protocol traffic
- Long-duration digital monitoring
- Production tests with changing pattern data
The host controller, chassis bandwidth and application buffer must be configured to sustain the required transfer rate.
Pattern Generation and Protocol Emulation
The PXIe-6536 can generate parallel digital patterns that emulate a controller, sensor or other external device. Engineers can define the data words and clocking behavior in software without depending on a fixed protocol implementation.
Typical pattern-generation tasks include:
- Sending initialization commands to a DUT
- Emulating digital image or display data
- Generating address and data sequences
- Simulating digital sensor outputs
- Creating repetitive functional test patterns
- Implementing proprietary parallel protocols
Image Sensor and Display Panel Testing
The 32-bit channel width and continuous PXI Express streaming capability make the PXIe-6536 suitable for interfacing with image sensors and display panels.
In image sensor applications, the module can acquire parallel pixel data and associated synchronization signals. In display applications, it can generate digital pattern data and control signals for functional testing.
The engineer must confirm that the device voltage, clock rate, channel count and electrical timing are within the PXIe-6536 specifications.
Change Detection Applications
Change detection allows the module to capture only meaningful digital transitions instead of sampling continuously at a fixed rate. This can reduce transferred data in applications where signal states remain unchanged for long periods.
Typical uses include:
- Monitoring digital status lines
- Capturing asynchronous control events
- Detecting encoder or position transitions
- Recording state changes in a digital subsystem
- Triggering additional measurements when an event occurs
Change detection does not replace external signal conditioning. Noisy or slowly transitioning signals may require suitable buffering or filtering before reaching the module.
Typical PXIe-6536 Applications
- High-speed pattern I/O
- Image sensor interface testing
- Display panel testing
- Parallel digital bus testing
- Custom protocol emulation
- Digital stimulus and response testing
- Change-detection acquisition
- FPGA and embedded controller validation
- Digital sensor simulation
- Hardware-in-the-loop testing
- Electronic component characterization
- Automated production testing
- Research and laboratory systems
PXIe-6536 Software Support
The PXIe-6536 is controlled through the NI-DAQmx driver. NI-DAQmx provides functions for channel configuration, sample-clock timing, digital generation, acquisition, triggering, buffering and data transfer.
Common development environments include:
- LabVIEW
- LabWindows/CVI
- Microsoft Visual C/C++
- .NET languages such as C# and Visual Basic .NET
- Python through compatible NI-DAQmx APIs
- NI TestStand integration
NI Measurement & Automation Explorer can be used to identify the module, verify driver installation, perform self-tests and confirm that the PXI system recognizes the hardware.
PXIe-6536 System Requirements
A complete PXIe-6536 system normally requires:
- A compatible PXI Express chassis
- An embedded PXI controller or external computer interface
- NI-DAQmx driver software
- A compatible 68-pin digital cable
- A terminal block, breakout accessory or custom fixture
- Appropriate application development software
For continuous 100 MB/s operation, the controller, PXI Express link and software buffers must provide sufficient sustained bandwidth.
Compatible Cables and Terminal Accessories
Common connection options include:
- SHC68-C68-D4 shielded digital cable
- C68-C68-D4 unshielded digital cable
- SCB-68A shielded connector block
- TBX-68 connector block
- CB-68LP unshielded connector block
- Custom high-speed digital interface fixtures
Shielded cabling is generally preferable in electrically noisy environments. Custom fixtures should maintain appropriate grounding and minimize unterminated signal branches.
Signal-Integrity Considerations
Although the maximum clock rate is 25 MHz, the digital signal edges can contain considerably higher-frequency content. Cable length, impedance discontinuities, grounding and DUT loading can therefore affect signal quality.
Recommended practices include:
- Use short, compatible digital cables
- Maintain a low-inductance ground connection
- Avoid unnecessary adapters and long signal stubs
- Select the correct logic family before connecting the DUT
- Confirm that the DUT does not exceed the input voltage range
- Verify setup-and-hold timing at the DUT connector
- Use a shielded terminal block in noisy environments
PXIe-6536 vs PXIe-6535
| Specification | PXIe-6535 | PXIe-6536 |
|---|---|---|
| Digital Channels | 32 | 32 |
| Maximum Clock Rate | 10 MHz | 25 MHz |
| Maximum Aggregate Streaming | 40 MB/s | 100 MB/s |
| Logic Levels | 2.5 V, 3.3 V and 5 V TTL compatible | 2.5 V, 3.3 V and 5 V TTL compatible |
| Direction Control | Per channel | Per channel |
| General Positioning | Lower-speed streaming digital I/O | Medium-speed streaming digital I/O |
The PXIe-6535 is suitable when a 10 MHz clock and 40 MB/s aggregate transfer rate are sufficient. The PXIe-6536 provides higher speed while retaining a similar digital I/O architecture.
PXIe-6536 vs PXIe-6537
| Specification | PXIe-6536 | PXIe-6537 |
|---|---|---|
| Digital Channels | 32 | 32 |
| Maximum Clock Rate | 25 MHz | 50 MHz |
| Maximum Aggregate Streaming | 100 MB/s | 200 MB/s |
| Logic Levels | 2.5 V, 3.3 V and 5 V TTL compatible | 2.5 V, 3.3 V and 5 V TTL compatible |
| Direction Control | Per channel | Per channel |
| General Positioning | 25 MHz digital streaming | Higher-speed 50 MHz digital streaming |
The PXIe-6537 is the direct higher-performance option when the application requires a clock rate above 25 MHz or aggregate streaming above 100 MB/s.
PXIe-6536 vs PXIe-6544
| Specification | PXIe-6536 | PXIe-6544 |
|---|---|---|
| Instrument Type | Streaming digital I/O | Digital waveform instrument |
| Digital Channels | 32 | 32 |
| Maximum Clock Rate | 25 MHz | 100 MHz |
| Logic Levels | 2.5 V, 3.3 V and 5 V TTL compatible | 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V |
| Driver | NI-DAQmx | NI-HSDIO |
| Primary Advantage | Continuous host-memory streaming | Higher-speed waveform generation and analysis |
The PXIe-6544 is preferable when higher sample rates, additional low-voltage logic families and digital waveform instrumentation are required. The PXIe-6536 is better suited to continuous NI-DAQmx streaming and flexible per-channel digital I/O.
Recommended Related Products
- PXIe-6535 – 32-channel, 10 MHz digital I/O module with up to 40 MB/s aggregate streaming.
- PXIe-6537 – 32-channel, 50 MHz digital I/O module with up to 200 MB/s aggregate streaming.
- PCIe-6536B – computer-based PCI Express version for systems that do not use a PXI chassis.
- PXIe-6544 – 32-channel, 100 MHz digital waveform instrument for higher-speed pattern applications.
- PXIe-6509 – high-channel-count static digital I/O module for control and monitoring applications.
- PXIe-1085 – high-bandwidth PXI Express chassis for multi-instrument automated test systems.
PXIe-6536 Selection Guidance
Before selecting the PXIe-6536, confirm that:
- The application requires no more than 32 digital channels
- The DUT uses single-ended digital signaling
- The DUT is compatible with 2.5 V, 3.3 V or 5 V TTL logic
- The required sample clock does not exceed 25 MHz
- The aggregate transfer requirement does not exceed 100 MB/s
- Per-channel direction control is required
- Continuous host-memory streaming is preferred
- The PXI controller can sustain the required DMA bandwidth
- The chassis provides a compatible PXI Express slot
Common Troubleshooting Checks
The Module Is Not Detected
Confirm that the PXIe-6536 is installed in a compatible PXI Express slot and that a supported NI-DAQmx driver is installed. Use NI MAX to check whether the module appears and passes its self-test.
Continuous Streaming Stops Unexpectedly
Check for buffer underflow during generation or buffer overflow during acquisition. Increase the host buffer size, transfer larger data blocks and verify that the controller can sustain the required transfer rate.
Digital Data Contains Timing Errors
Verify the sample clock source, active edge, logic family and channel direction. Check cable length, grounding and DUT setup-and-hold requirements.
The DUT Does Not Recognize Generated Data
Confirm that the selected 2.5 V, 3.3 V or 5 V TTL-compatible logic setting matches the DUT. Verify the generated pattern, bit order, port mapping and handshake configuration.
Change Detection Produces Too Many Events
Check whether change detection is configured for rising edges, falling edges or both. Inspect the input signal for noise or slow transitions that may cause additional edge detections.
An External Clock Is Not Recognized
Verify that the external clock is connected to a clock-capable PFI terminal and remains within the supported frequency and voltage limits. Confirm the terminal and edge selection in NI-DAQmx.
Frequently Asked Questions
What is the PXIe-6536 used for?
The PXIe-6536 is used for continuous digital data streaming, pattern generation, digital acquisition, change detection, protocol emulation and automated device testing.
How many digital channels does the PXIe-6536 provide?
It provides 32 bidirectional single-ended digital channels with per-channel direction control.
What is the maximum clock rate?
The maximum sample clock rate is 25 MHz.
What does the 100 MB/s specification mean?
It is the aggregate transfer rate for a 32-bit-wide sample stream operating at 25 MHz. Each individual digital line operates at up to 25 Mbit/s.
Which logic levels are supported?
The PXIe-6536 supports 2.5 V, 3.3 V and 5 V TTL-compatible logic families.
Can each channel have a different direction?
Yes. Every digital data channel can be independently configured as an input or output.
Does the PXIe-6536 support continuous streaming?
Yes. It uses DMA and the PXI Express bus to continuously transfer generated or acquired data between the module and host memory.
Does the PXIe-6536 have deep onboard memory?
No. It uses a 2,048-sample onboard FIFO and is primarily designed for continuous streaming rather than storing complete long waveforms onboard.
Which driver controls the PXIe-6536?
The module is controlled through the NI-DAQmx driver.
What is the PXIe-6536 part number?
The standard NI part number is 779988-01.
Can the PXIe-6536 operate independently?
No. It requires a compatible PXI Express chassis and an embedded controller or external computer interface.
What is the main difference between PXIe-6536 and PXIe-6537?
The PXIe-6536 operates at up to 25 MHz and 100 MB/s, while the PXIe-6537 increases performance to 50 MHz and 200 MB/s.
Why Choose the PXIe-6536?
The PXIe-6536 is a practical choice for applications requiring continuous 32-bit digital streaming at moderate speeds. It combines 32 independently configurable channels, selectable logic levels, multiple timing modes and up to 100 MB/s aggregate throughput.
Its NI-DAQmx support and PXI Express architecture make it suitable for both laboratory development and automated production systems involving pattern I/O, image devices, display panels and custom digital interfaces.
Request a Quote for the PXIe-6536
Contact us for current availability, lead time and project pricing for the NI PXIe-6536 High-Speed Digital I/O Module, part number 779988-01.
We can also help identify compatible PXI Express chassis, controllers, SHC68-C68-D4 cables, terminal blocks and related digital I/O modules for your test system.
