{"id":36614,"date":"2026-09-11T20:21:36","date_gmt":"2026-09-11T12:21:36","guid":{"rendered":"https:\/\/pxisource.com\/?post_type=product&#038;p=36614"},"modified":"2026-09-11T20:31:33","modified_gmt":"2026-09-11T12:31:33","slug":"pxi-6651","status":"publish","type":"product","link":"https:\/\/pxisource.com\/ru\/product\/pxi-6651\/","title":{"rendered":"PXI-6651"},"content":{"rendered":"<h3>PXI-6651 Slave Timing and Synchronization Module<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <strong>NI PXI-6651<\/strong> is a PXI timing and synchronization module designed primarily for use as a slave device in multichassis PXI systems. It receives externally generated clock and trigger signals and routes them to instruments through the PXI backplane, helping multiple modules and chassis operate from coordinated timing references.<\/p>\n<p>The PXI-6651 provides one front-panel CLKIN connection, two bidirectional programmable function interface connections and access to the PXI trigger bus and PXI star trigger lines. Its external clock input accepts sine- or square-wave signals from 1 MHz to 105 MHz, while its PFI terminals can receive or generate signals from DC to 105 MHz.<\/p>\n<p>Unlike the PXI-6652 and PXI-6653 master timing modules, the PXI-6651 does not include an onboard TCXO, OCXO, direct digital synthesis clock generator or front-panel CLKOUT connector. It is optimized for receiving and distributing timing signals generated by a master module or another suitable external timing source.<\/p>\n<h3>Key Features of the PXI-6651<\/h3>\n<ul>\n<li>PXI slave timing and synchronization module<\/li>\n<li>Designed for multichassis PXI clock and trigger distribution<\/li>\n<li>1 MHz to 105 MHz CLKIN frequency range<\/li>\n<li>Accepts sine- and square-wave clock inputs<\/li>\n<li>400 mVp-p to 5 Vp-p CLKIN operating range<\/li>\n<li>Two bidirectional programmable function interface connections<\/li>\n<li>DC to 105 MHz PFI input and output operation<\/li>\n<li>Software-selectable PFI input impedance<\/li>\n<li>Programmable PFI input thresholds<\/li>\n<li>Routing support for PXI_TRIG&lt;0..7&gt;<\/li>\n<li>Routing support for PXI_STAR&lt;0..12&gt;<\/li>\n<li>External 10 MHz reference distribution to PXI_CLK10_IN<\/li>\n<li>Synchronous and asynchronous trigger routing<\/li>\n<li>Two front-panel status indicators<\/li>\n<li>NI-Sync driver support<\/li>\n<li>Single-slot 3U PXI form factor<\/li>\n<\/ul>\n<h2>PXI-6651 Technical Specifications<\/h2>\n<table>\n<tbody>\n<tr>\n<th>Product Model<\/th>\n<td>PXI-6651<\/td>\n<\/tr>\n<tr>\n<th>Part Number<\/th>\n<td>778725-01<\/td>\n<\/tr>\n<tr>\n<th>Product Type<\/th>\n<td>PXI slave timing and synchronization module<\/td>\n<\/tr>\n<tr>\n<th>Primary Function<\/th>\n<td>\u0412\u043d\u0435\u0448\u043d\u044f\u044f \u043c\u0430\u0440\u0448\u0440\u0443\u0442\u0438\u0437\u0430\u0446\u0438\u044f \u0442\u0430\u043a\u0442\u043e\u0432\u044b\u0445 \u0441\u0438\u0433\u043d\u0430\u043b\u043e\u0432 \u0438 \u0442\u0440\u0438\u0433\u0433\u0435\u0440\u043e\u0432<\/td>\n<\/tr>\n<tr>\n<th>CLKIN Frequency Range<\/th>\n<td>1 MHz to 105 MHz, sine or square wave<\/td>\n<\/tr>\n<tr>\n<th>CLKIN Voltage Range<\/th>\n<td>400 mVp-p to 5 Vp-p<\/td>\n<\/tr>\n<tr>\n<th>CLKIN Absolute Maximum<\/th>\n<td>6 Vp-p<\/td>\n<\/tr>\n<tr>\n<th>CLKIN Input Coupling<\/th>\n<td>AC coupled<\/td>\n<\/tr>\n<tr>\n<th>CLKIN Input Impedance<\/th>\n<td>50 \u03a9 nominal<\/td>\n<\/tr>\n<tr>\n<th>Reference Clock Replacement<\/th>\n<td>External 10 MHz signal can replace PXI_CLK10<\/td>\n<\/tr>\n<tr>\n<th>PFI Connections<\/th>\n<td>2, PFI 0 and PFI 1<\/td>\n<\/tr>\n<tr>\n<th>PFI Direction<\/th>\n<td>Individually programmable as input or output<\/td>\n<\/tr>\n<tr>\n<th>PFI Frequency Range<\/th>\n<td>DC to 105 MHz<\/td>\n<\/tr>\n<tr>\n<th>PFI Input Coupling<\/th>\n<td>DC coupled<\/td>\n<\/tr>\n<tr>\n<th>PFI Input Impedance<\/th>\n<td>50 \u03a9 nominal or 1 k\u03a9 \u00b110% in parallel with 35 pF, software selectable<\/td>\n<\/tr>\n<tr>\n<th>PFI Input Voltage<\/th>\n<td>0 V to 5 V<\/td>\n<\/tr>\n<tr>\n<th>PFI Input Threshold<\/th>\n<td>0 V to 4.3 V, software selectable<\/td>\n<\/tr>\n<tr>\n<th>Threshold Resolution<\/th>\n<td>16.8 mV, 8-bit<\/td>\n<\/tr>\n<tr>\n<th>PFI Output Level<\/th>\n<td>0 V to 1.6 V into 50 \u03a9; 0 V to 3.3 V into an open circuit, typical<\/td>\n<\/tr>\n<tr>\n<th>PXI \u0422\u0440\u0438\u0433\u0433\u0435\u0440\u043d\u0430\u044f \u0448\u0438\u043d\u0430<\/th>\n<td>PXI_TRIG&lt;0..7&gt;<\/td>\n<\/tr>\n<tr>\n<th>PXI Star Trigger Access<\/th>\n<td>PXI_STAR&lt;0..12&gt;<\/td>\n<\/tr>\n<tr>\n<th>PXI Star Output Skew<\/th>\n<td>300 ps typical at the module backplane connector<\/td>\n<\/tr>\n<tr>\n<th>Synchronous Output-to-Output Skew<\/th>\n<td>500 ps typical<\/td>\n<\/tr>\n<tr>\n<th>Front-Panel Connectors<\/th>\n<td>3 \u00d7 50 \u03a9 male SMB: CLKIN, PFI 0 and PFI 1<\/td>\n<\/tr>\n<tr>\n<th>Front-Panel Indicators<\/th>\n<td>Access and Active tricolor LEDs<\/td>\n<\/tr>\n<tr>\n<th>Onboard Precision Oscillator<\/th>\n<td>\u041d\u0438\u0447\u0435\u0433\u043e<\/td>\n<\/tr>\n<tr>\n<th>Direct Digital Synthesis<\/th>\n<td>Not supported<\/td>\n<\/tr>\n<tr>\n<th>Front-Panel CLKOUT<\/th>\n<td>Not provided<\/td>\n<\/tr>\n<tr>\n<th>Software Driver<\/th>\n<td>NI-Sync<\/td>\n<\/tr>\n<tr>\n<th>Chassis Requirement<\/th>\n<td>One 3U CompactPCI or PXI slot; Slot 2 recommended for full functionality<\/td>\n<\/tr>\n<tr>\n<th>Operating Temperature<\/th>\n<td>0\u00b0C to 55\u00b0C<\/td>\n<\/tr>\n<tr>\n<th>Operating Humidity<\/th>\n<td>10% to 90%, noncondensing<\/td>\n<\/tr>\n<tr>\n<th>Storage Temperature<\/th>\n<td>-20\u00b0C to 70\u00b0C<\/td>\n<\/tr>\n<tr>\n<th>Maximum Operating Altitude<\/th>\n<td>2,000 m at 25\u00b0C ambient temperature<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>The 1 MHz to 105 MHz CLKIN specification describes the range supported by the input circuitry. When CLKIN is routed directly to replace the chassis PXI_CLK10 reference without a PLL, the applied signal must be a compatible 10 MHz clock meeting the PXI timing requirements.<\/p>\n<h3>Slave Timing Architecture<\/h3>\n<p>The PXI-6651 is primarily a routing module. It does not generate a precision timing reference independently; instead, it accepts a clock or trigger from an external master and distributes that signal to resources inside its local chassis.<\/p>\n<p>This architecture is useful when a test system contains several PXI chassis. A master timing module can establish the system reference, while a PXI-6651 installed in each secondary chassis receives and redistributes the clock and trigger signals.<\/p>\n<h3>External CLKIN Connection<\/h3>\n<p>The front-panel CLKIN connector accepts sine- or square-wave signals with fundamental frequencies from 1 MHz to 105 MHz. The input is AC coupled and has a nominal impedance of 50 \u03a9.<\/p>\n<p>CLKIN can be routed to the chassis PXI_CLK10_IN connection so that compatible instruments in the chassis use an externally supplied reference. This enables the secondary chassis to derive its timing from the same reference used by the rest of the test system.<\/p>\n<p>When distributing a clock between chassis, use 50 \u03a9 cabling, maintain suitable signal amplitude and avoid unnecessary adapters or unterminated branches. Cable delay and splitter loss must be included in the overall synchronization design.<\/p>\n<h3>Two Bidirectional PFI Connections<\/h3>\n<p>The PXI-6651 provides two programmable function interface connections identified as PFI 0 and PFI 1. Each connection can be configured independently as an input or output.<\/p>\n<p>A PFI input can receive an external start trigger, reference event or clock signal. A PFI output can export a trigger received from the PXI backplane or another front-panel terminal. PFI 0 can also act as a clock source for synchronous routing operations.<\/p>\n<p>The PFI input threshold can be adjusted through software from 0 V to 4.3 V. This capability helps the module recognize signals from different digital logic families while remaining within its permitted electrical limits.<\/p>\n<h3>PXI Trigger Bus Routing<\/h3>\n<p>The module provides access to all eight PXI trigger bus lines, PXI_TRIG&lt;0..7&gt;. These shared backplane lines are commonly used to distribute start triggers, reference triggers, events and other synchronization signals among instruments in one chassis.<\/p>\n<p>The PXI-6651 can route signals between its PFI connections and the trigger bus. It can also route a signal received from one backplane resource to another supported destination, subject to the routing rules and resource availability defined by NI-Sync.<\/p>\n<h3>PXI Star Trigger Distribution<\/h3>\n<p>When installed in the chassis system timing slot, normally Slot 2, the PXI-6651 can access the PXI star trigger lines. PXI star topology provides dedicated point-to-point connections between the timing slot and compatible peripheral slots.<\/p>\n<p>The official specifications list 300 ps typical skew between PXI star outputs at the timing module\u2019s backplane connector. Actual instrument-to-instrument alignment also depends on chassis characteristics, receiving-device circuitry, cable delay and instrument configuration.<\/p>\n<h3>Synchronous and Asynchronous Routing<\/h3>\n<p>Asynchronous routing transfers an incoming event through the routing hardware without aligning it to a reference-clock edge. This approach can provide low latency and is useful when the absolute arrival time of the external trigger must be preserved.<\/p>\n<p>Synchronous routing resamples or aligns a trigger to the selected synchronization clock. This can improve output-to-output consistency and reduce uncertainty between trigger destinations, but it adds clock-dependent timing behavior that must be considered in the test sequence.<\/p>\n<p>Select the routing method according to whether the application prioritizes minimum latency or alignment to a common clock domain.<\/p>\n<h2>PXI-6651 Part Number and Accessories<\/h2>\n<table>\n<tbody>\n<tr>\n<th>Item<\/th>\n<th>Part Number or Type<\/th>\n<th>\u041e\u043f\u0438\u0441\u0430\u043d\u0438\u0435<\/th>\n<\/tr>\n<tr>\n<td>PXI-6651<\/td>\n<td>778725-01<\/td>\n<td>PXI slave timing and synchronization module<\/td>\n<\/tr>\n<tr>\n<td>Clock Cable<\/td>\n<td>50 \u03a9 SMB coaxial cable<\/td>\n<td>Connects a master reference-clock output to the PXI-6651 CLKIN terminal<\/td>\n<\/tr>\n<tr>\n<td>Trigger Cable<\/td>\n<td>50 \u03a9 SMB coaxial cable<\/td>\n<td>Connects master and slave PFI terminals for trigger distribution<\/td>\n<\/tr>\n<tr>\n<td>Master Timing Module<\/td>\n<td>PXI-6652<\/td>\n<td>TCXO-based master timing module with clock generation and six PFI connections<\/td>\n<\/tr>\n<tr>\n<td>Precision Master Timing Module<\/td>\n<td>PXI-6653<\/td>\n<td>OCXO-based master timing module for higher-stability timing applications<\/td>\n<\/tr>\n<tr>\n<td>PXI \u0428\u0430\u0441\u0441\u0438<\/td>\n<td>Compatible 3U PXI chassis<\/td>\n<td>Provides the PXI backplane, PXI trigger bus and system timing slot<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Accessory selection depends on cable length, connector gender, signal frequency, desired clock amplitude and the physical arrangement of the chassis. Verify that each cable presents the required 50 \u03a9 transmission-line environment at the operating frequency.<\/p>\n<p>Because the PXI-6651 does not have a CLKOUT connector, the clock must be supplied to its CLKIN terminal from a master timing device or another compatible external source. Trigger signals are normally transferred through PFI 0 or PFI 1.<\/p>\n<h3>Clock and Trigger Cable Planning<\/h3>\n<p>Equal-length cables help reduce deterministic delay differences between parallel chassis. If several slave chassis receive the same clock or trigger through a passive splitter, account for splitter insertion loss, impedance matching and differences among individual cable assemblies.<\/p>\n<p>Cable propagation delay does not normally prevent synchronization, but it can create a fixed phase or event-time offset. Precision systems should characterize this offset and compensate for it in software or through calibrated cable selection.<\/p>\n<h3>\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u043d\u043e\u0433\u043e \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0435\u043d\u0438\u044f<\/h3>\n<p>The PXI-6651 is configured using the <strong>NI-Sync<\/strong> driver. NI-Sync provides programming interfaces for selecting routing sources and destinations, configuring PFI electrical characteristics, replacing the chassis reference clock and monitoring module status.<\/p>\n<p>Applications can use NI-Sync from supported NI development environments such as LabVIEW and LabWindows\/CVI, as well as supported text-based programming environments. Driver and operating-system compatibility should be confirmed before installing this legacy module in a replacement system.<\/p>\n<h3>What the PXI-6651 Does Not Include<\/h3>\n<ul>\n<li>No onboard OCXO precision oscillator<\/li>\n<li>No onboard TCXO reference oscillator<\/li>\n<li>No direct digital synthesis clock generator<\/li>\n<li>No dedicated front-panel CLKOUT connector<\/li>\n<li>No GPS receiver<\/li>\n<li>No IRIG-B synchronization interface<\/li>\n<li>No IEEE 1588 network synchronization capability<\/li>\n<\/ul>\n<p>These distinctions are important when selecting a timing module. The PXI-6651 is appropriate when a system already has a master reference and requires clock and trigger distribution in a secondary PXI chassis.<\/p>\n<h2>PXI-6651 Applications<\/h2>\n<ul>\n<li>Multichassis PXI synchronization<\/li>\n<li>External 10 MHz reference-clock distribution<\/li>\n<li>PXI trigger routing<\/li>\n<li>PXI star trigger distribution<\/li>\n<li>Coordinated data acquisition<\/li>\n<li>Synchronized digitizer systems<\/li>\n<li>Waveform generation and acquisition alignment<\/li>\n<li>Automated production testing<\/li>\n<li>Hardware-in-the-loop testing<\/li>\n<li>Research and physics instrumentation<\/li>\n<li>Multichannel stimulus-and-response systems<\/li>\n<li>Legacy PXI system maintenance<\/li>\n<\/ul>\n<h3>Multichassis PXI Synchronization<\/h3>\n<p>A large test platform may require more instrument slots than one PXI chassis can provide. In this configuration, a master timing module distributes a common reference clock and trigger signals to PXI-6651 modules installed in secondary chassis.<\/p>\n<p>Each PXI-6651 routes the received reference to its local PXI backplane. Instruments distributed among the chassis can then execute acquisitions or stimulus operations from coordinated clock and trigger resources.<\/p>\n<h3>Synchronized Data Acquisition<\/h3>\n<p>Data acquisition systems often require multiple devices to begin sampling in response to the same event. The PXI-6651 can import a trigger through a PFI terminal and distribute it through PXI_TRIG or PXI_STAR to compatible modules.<\/p>\n<p>When sample-clock alignment is also required, distribute a common reference clock to every chassis and configure each measurement device to derive its internal timing from that reference.<\/p>\n<h3>Digitizer and Oscilloscope Systems<\/h3>\n<p>PXI digitizers installed in separate chassis can use a shared frequency reference and coordinated triggers to improve repeatability between acquisitions. This is useful for high-channel-count waveform capture, transient analysis and distributed electronic testing.<\/p>\n<p>The final synchronization accuracy depends on the complete signal path, including the master source, timing modules, chassis backplanes, cables and digitizer timebases.<\/p>\n<h3>Waveform Generation and Stimulus Systems<\/h3>\n<p>Signal generators in multiple chassis can be coordinated with measurement hardware by using a common frequency reference and shared start event. The PXI-6651 supplies the clock and trigger-routing resources needed in a slave chassis.<\/p>\n<p>Some instruments require additional phase-alignment or synchronization commands after receiving a shared reference. Follow the instrument-specific synchronization procedure instead of assuming that reference-clock sharing alone guarantees phase alignment.<\/p>\n<h3>Automated Production Testing<\/h3>\n<p>In production systems, deterministic trigger distribution helps coordinate switching, stimulus generation, measurement and device-handler operations. A centralized timing design also makes the test sequence easier to reproduce across stations.<\/p>\n<p>The PXI-6651 is particularly useful when maintaining established PXI systems whose software and fixtures were designed around NI-Sync and the PXI-665x family.<\/p>\n<h3>\u0421\u0438\u0441\u0442\u0435\u043c\u044b \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u043e-\u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u043d\u043e\u0433\u043e \u043c\u043e\u0434\u0435\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f<\/h3>\n<p>Hardware-in-the-loop systems may distribute simulation, acquisition, bus communication and fault-insertion hardware across several PXI chassis. A shared clock and trigger architecture reduces timing uncertainty between these subsystems.<\/p>\n<p>The PXI-6651 can act as the timing receiver in each secondary chassis while a compatible master timing device provides the primary system reference.<\/p>\n<h3>PXI-6651 Multichassis Architecture<\/h3>\n<h4>Master Chassis<\/h4>\n<p>The master chassis contains the timing source, such as a PXI-6652, PXI-6653 or another compatible clock and trigger generator. It exports a reference clock and one or more synchronization events.<\/p>\n<h4>Slave Chassis<\/h4>\n<p>Each slave chassis contains a PXI-6651. The module receives the clock through CLKIN and receives or exports trigger events through PFI 0 and PFI 1.<\/p>\n<h4>Local Instruments<\/h4>\n<p>Instruments inside the slave chassis obtain the reference and trigger signals through PXI_CLK10, PXI_TRIG or PXI_STAR. Each instrument must be configured to use the correct backplane resources.<\/p>\n<h4>Software Control<\/h4>\n<p>NI-Sync configures the PXI-6651 routing paths. Instrument-specific drivers then configure the digitizers, generators, DAQ modules or other devices to consume the distributed timing signals.<\/p>\n<h2>PXI-6651 Installation Workflow<\/h2>\n<h4>Step 1: Verify System Compatibility<\/h4>\n<p>Confirm that the chassis provides a compatible 3U PXI or CompactPCI slot and that the computer, operating system and NI-Sync version support the PXI-6651.<\/p>\n<h4>Step 2: Select the Chassis Slot<\/h4>\n<p>Install the module in PXI Slot 2 when the application requires full access to PXI star trigger resources and PXI_CLK10_IN. Installation in another compatible slot may limit timing functionality.<\/p>\n<h4>Step 3: Install NI-Sync<\/h4>\n<p>Install the appropriate NI-Sync driver before installing or configuring the hardware. Restart the controller if required by the driver installation process.<\/p>\n<h4>Step 4: Power Down the Chassis<\/h4>\n<p>Turn off and unplug the PXI chassis. Follow electrostatic-discharge precautions before handling the module, and avoid touching exposed connector pins.<\/p>\n<h4>Step 5: Install the Module<\/h4>\n<p>Remove the selected slot\u2019s filler panel, align the PXI-6651 with the card guides and use the injector\/ejector handle to seat it fully. Secure the front panel to the chassis rail.<\/p>\n<h4>Step 6: Connect the Reference Clock<\/h4>\n<p>Connect the master clock source to CLKIN using a suitable 50 \u03a9 SMB cable. When replacing PXI_CLK10 directly, configure the source for a compatible 10 MHz signal and verify its amplitude and frequency accuracy.<\/p>\n<h4>Step 7: Connect Trigger Lines<\/h4>\n<p>Connect the master trigger output to PFI 0 or PFI 1. If identical events must reach several chassis, use a properly designed distribution network and account for cable and splitter delays.<\/p>\n<h4>Step 8: Detect the Module<\/h4>\n<p>Power on the chassis and verify that the module appears correctly in NI Measurement &amp; Automation Explorer. Check the Access and Active indicators for unexpected status conditions.<\/p>\n<h4>Step 9: Configure Timing Routes<\/h4>\n<p>Use NI-Sync to select the CLKIN, PFI, PXI_TRIG, PXI_STAR and PXI_CLK10_IN routing required by the application. Avoid configuring multiple outputs to drive the same physical resource.<\/p>\n<h4>Step 10: Configure Receiving Instruments<\/h4>\n<p>Set every receiving instrument to use the intended reference clock and trigger terminal. A route configured on the PXI-6651 is not sufficient if the destination instrument is still configured for an internal clock or software trigger.<\/p>\n<h4>Step 11: Validate Synchronization<\/h4>\n<p>Run a controlled test and measure the timing relationship among chassis. Verify clock frequency, trigger delay, acquisition alignment and repeatability before deploying the system.<\/p>\n<h3>Installation Best Practices<\/h3>\n<ul>\n<li>Use PXI Slot 2 for full timing functionality<\/li>\n<li>Use impedance-controlled 50 \u03a9 coaxial cables<\/li>\n<li>Keep parallel synchronization cables matched in length<\/li>\n<li>Avoid unterminated signal branches<\/li>\n<li>Document all NI-Sync routes and terminal assignments<\/li>\n<li>Configure the clock network before arming acquisition devices<\/li>\n<li>Verify that only one source drives each backplane line<\/li>\n<li>Characterize fixed cable and routing delays<\/li>\n<li>Retain filler panels to maintain chassis airflow<\/li>\n<\/ul>\n<h2>PXI-6651 Troubleshooting<\/h2>\n<h4>The PXI-6651 Is Not Detected<\/h4>\n<p>Confirm that the module is fully seated in the chassis and that NI-Sync is installed. Check chassis power, controller communication and module visibility in NI Measurement &amp; Automation Explorer.<\/p>\n<h4>PXI Star Trigger Routes Are Unavailable<\/h4>\n<p>Verify that the PXI-6651 is installed in the chassis system timing slot, normally Slot 2. PXI star trigger lines are point-to-point resources connected to that slot and are not fully accessible from an ordinary peripheral slot.<\/p>\n<h4>The External Clock Is Not Recognized<\/h4>\n<p>Check that the CLKIN frequency is between 1 MHz and 105 MHz and that the amplitude remains within the permitted range. Inspect the SMB connector, cable continuity, source configuration and 50 \u03a9 termination.<\/p>\n<h4>The Chassis Does Not Lock to the External Reference<\/h4>\n<p>The PXI-6651 does not contain the PLL architecture found in the PXI-6652 and PXI-6653. When CLKIN is used to replace PXI_CLK10 directly, supply a compatible 10 MHz reference that meets the applicable PXI frequency requirements.<\/p>\n<h4>A PFI Input Does Not Detect the Trigger<\/h4>\n<p>Verify the selected PFI direction, input impedance and programmable threshold. Measure the signal at the PXI-6651 connector and confirm that the voltage remains between the supported limits.<\/p>\n<h4>A PFI Output Has Lower Amplitude Than Expected<\/h4>\n<p>PFI output amplitude depends on loading. The typical high level is approximately 1.6 V into 50 \u03a9 and 3.3 V into an open circuit. Confirm that the receiving equipment is compatible with the configured load and voltage.<\/p>\n<h4>Trigger Timing Differs Between Chassis<\/h4>\n<p>Check cable lengths, splitter paths, routing modes and destination configurations. Different cable propagation delays or a mixture of synchronous and asynchronous routes can create deterministic offsets.<\/p>\n<h4>Trigger Timing Is Not Repeatable<\/h4>\n<p>Use synchronous routing when triggers need to align with a shared clock. Confirm that all chassis receive a stable common reference and that every destination instrument uses the intended timing source.<\/p>\n<h4>The Active LED Is Red<\/h4>\n<p>A red Active indicator can identify a timing fault such as a stopped PXI_CLK10 resource. Check the incoming reference, chassis clock state and NI-Sync error information before continuing the test.<\/p>\n<h4>NI-Sync Reports a Routing Conflict<\/h4>\n<p>Review the complete routing configuration. A PXI trigger line, star line or PFI destination may already be reserved or driven by another device. Disconnect the conflicting route before creating the new path.<\/p>\n<h4>The Module Works but Instruments Remain Unsynchronized<\/h4>\n<p>Confirm the configuration of the receiving instruments. They must be programmed to use the distributed reference and trigger resources. Also verify whether the instrument family requires a separate synchronization, phase-reset or initialization command.<\/p>\n<h2>PXI-6651 Comparison<\/h2>\n<table>\n<tbody>\n<tr>\n<th>\u041c\u043e\u0434\u0435\u043b\u044c<\/th>\n<th>Timing Role<\/th>\n<th>Reference Source<\/th>\n<th>Front-Panel Timing I\/O<\/th>\n<th>Best Suited For<\/th>\n<\/tr>\n<tr>\n<td>PXI-6651<\/td>\n<td>Slave<\/td>\n<td>External clock<\/td>\n<td>CLKIN and 2 PFI<\/td>\n<td>Receiving and routing timing in secondary PXI chassis<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-6652\/\">PXI-6652<\/a><\/td>\n<td>Master or timing distributor<\/td>\n<td>10 MHz TCXO, DDS or external reference<\/td>\n<td>CLKIN, CLKOUT and 6 PFI<\/td>\n<td>General-purpose multichassis master timing<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-6653\/\">PXI-6653<\/a><\/td>\n<td>Precision master<\/td>\n<td>10 MHz OCXO, DDS or external reference<\/td>\n<td>CLKIN, CLKOUT and 6 PFI<\/td>\n<td>Higher-stability PXI clock generation and distribution<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-6674t\/\">PXIe-6674T<\/a><\/td>\n<td>PXI Express timing module<\/td>\n<td>Modern precision timing architecture<\/td>\n<td>Model-specific clock and trigger I\/O<\/td>\n<td>High-performance PXI Express synchronization<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-6683h\/\">PXI-6683H<\/a><\/td>\n<td>Time-reference synchronization<\/td>\n<td>GPS, IRIG-B and network time sources<\/td>\n<td>Time and event interfaces<\/td>\n<td>Absolute time, GPS and IEEE 1588 applications<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXI-6651 vs PXI-6652<\/h3>\n<p>The PXI-6651 is primarily a slave routing module, while the PXI-6652 can operate as a master clock source. The PXI-6652 includes a 10 MHz TCXO, direct digital synthesis, six PFI connections and a front-panel CLKOUT.<\/p>\n<p>Select the PXI-6651 for secondary chassis that already receive timing from a master. Select the PXI-6652 when the chassis must generate and export its own programmable clock and trigger signals.<\/p>\n<h3>PXI-6651 vs PXI-6653<\/h3>\n<p>The PXI-6653 adds an oven-controlled crystal oscillator for applications requiring greater reference stability. It also provides clock generation, CLKOUT and six PFI terminals.<\/p>\n<p>The PXI-6651 is generally more appropriate for slave chassis, while the PXI-6653 is better suited to serving as the high-stability master of an established PXI-665x synchronization network.<\/p>\n<h3>PXI-6651 vs PXIe-6674T<\/h3>\n<p>The PXI-6651 belongs to the conventional PXI platform and supports legacy PXI trigger and clock resources. The PXIe-6674T is designed for PXI Express timing systems and provides a newer synchronization architecture.<\/p>\n<p>Selection should be based on chassis type, timing-slot compatibility, installed instrumentation, driver support and the clock-generation features required by the application.<\/p>\n<h3>PXI-6651 vs PXI-6683H<\/h3>\n<p>The PXI-6651 distributes relative clocks and triggers but does not provide an absolute time reference. The PXI-6683H is designed for applications requiring GPS, IRIG-B or IEEE 1588-based synchronization.<\/p>\n<p>Choose the PXI-6651 for deterministic signal routing inside a conventional PXI system. Choose a PXI-6683H-class device when measurements must be correlated to universal or network-distributed time.<\/p>\n<h3>Selecting the Right Timing Module<\/h3>\n<p>Choose the PXI-6651 when the test system already includes a suitable master clock and needs an economical timing receiver for a secondary PXI chassis. Its two PFI terminals and backplane-routing resources support the core clock and trigger requirements of many multichassis systems.<\/p>\n<p>Choose the PXI-6652 or PXI-6653 when onboard clock generation is required. Consider a newer PXI Express timing module when developing a new PXIe system or when advanced timing features and long-term software support are priorities.<\/p>\n<h3>Recommended Related Products<\/h3>\n<ul>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-6652\/\">PXI-6652 TCXO Timing and Synchronization Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-6653\/\">PXI-6653 OCXO Timing and Synchronization Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-6674t\/\">PXIe-6674T Timing and Synchronization Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-6683h\/\">PXI-6683H GPS and IEEE 1588 Timing Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product-category\/%d0%bd%d0%b8\/pxi-%d1%81%d0%b8%d1%81%d1%82%d0%b5%d0%bc%d1%81\/%d0%bc%d0%be%d0%b4%d1%83%d0%bb%d0%b8-pxi\/\">View More NI PXI and PXI Express Modules<\/a><\/li>\n<\/ul>\n<h3>Why Choose the PXI-6651?<\/h3>\n<ul>\n<li>Provides clock and trigger routing for slave PXI chassis<\/li>\n<li>Accepts external clocks from 1 MHz to 105 MHz<\/li>\n<li>Supports direct external 10 MHz PXI_CLK10 replacement<\/li>\n<li>Provides two bidirectional PFI connections<\/li>\n<li>Supports all eight PXI trigger bus lines<\/li>\n<li>Accesses PXI star trigger resources from the timing slot<\/li>\n<li>Supports synchronous and asynchronous event routing<\/li>\n<li>Integrates with established NI-Sync applications<\/li>\n<li>Fits one 3U PXI slot<\/li>\n<li>Supports maintenance and expansion of legacy multichassis systems<\/li>\n<\/ul>\n<h2>Frequently Asked Questions<\/h2>\n<h4>What is the PXI-6651?<\/h4>\n<p>The PXI-6651 is a PXI slave timing and synchronization module used to receive and route external clock and trigger signals within multichassis test systems.<\/p>\n<h4>What is the PXI-6651 part number?<\/h4>\n<p>The standard NI part number for the PXI-6651 is <strong>778725-01<\/strong>.<\/p>\n<h4>Does the PXI-6651 generate its own precision clock?<\/h4>\n<p>No. The PXI-6651 does not contain an onboard OCXO, TCXO or direct digital synthesis clock generator. It routes timing signals supplied by an external source.<\/p>\n<h4>What is the CLKIN frequency range?<\/h4>\n<p>The CLKIN connector accepts sine- or square-wave signals with fundamental frequencies from 1 MHz to 105 MHz.<\/p>\n<h4>Can the PXI-6651 replace the chassis PXI_CLK10 reference?<\/h4>\n<p>Yes. An external 10 MHz signal connected to CLKIN can be routed to PXI_CLK10_IN to replace the chassis reference, provided the source meets the required PXI specifications.<\/p>\n<h4>How many PFI connections does the PXI-6651 provide?<\/h4>\n<p>It provides two bidirectional PFI connections, PFI 0 and PFI 1. Each can be configured individually as an input or output.<\/p>\n<h4>What is the PFI frequency range?<\/h4>\n<p>The PFI input and output circuitry supports signals from DC to 105 MHz.<\/p>\n<h4>Does the PXI-6651 support PXI star triggers?<\/h4>\n<p>Yes. It can route signals through PXI_STAR&lt;0..12&gt; when installed in the chassis system timing slot.<\/p>\n<h4>Which slot should be used?<\/h4>\n<p>NI recommends PXI Slot 2 for full functionality, including access to PXI star trigger and reference-clock routing resources.<\/p>\n<h4>Does the PXI-6651 have a CLKOUT connector?<\/h4>\n<p>No. The PXI-6651 front panel provides CLKIN, PFI 0 and PFI 1. Dedicated CLKOUT is available on the PXI-6652 and PXI-6653.<\/p>\n<h4>Which software controls the PXI-6651?<\/h4>\n<p>The module is configured through the NI-Sync driver, which manages clock routing, trigger routing, PFI settings and supported synchronization operations.<\/p>\n<h4>Can the PXI-6651 provide GPS or IEEE 1588 synchronization?<\/h4>\n<p>No. It does not contain GPS, IRIG-B or IEEE 1588 interfaces. Applications requiring absolute time synchronization should use a suitable time-reference module such as the PXI-6683H.<\/p>\n<h4>Can multiple PXI-6651 modules be used in one system?<\/h4>\n<p>Yes. A master timing source can distribute reference clocks and triggers to PXI-6651 modules installed in multiple slave chassis. Cable topology, source loading and timing offsets must be considered during system design.<\/p>\n<h3>Request a Quote for the PXI-6651<\/h3>\n<p>Contact us for current availability, lead time and project pricing for the <strong>NI PXI-6651 Slave Timing and Synchronization Module<\/strong>. We can also help identify compatible PXI chassis, 50 \u03a9 SMB cables, master timing modules and replacement synchronization hardware for your test system.<\/p>","protected":false},"excerpt":{"rendered":"<p>PXI-6651 Slave Timing and Synchronization Module The NI PXI-6651 is a PXI timing and synchronization module designed primarily for use<\/p>","protected":false},"featured_media":36611,"template":"","meta":{"_acf_changed":false},"product_brand":[18],"product_cat":[667],"product_tag":[],"class_list":["post-36614","product","type-product","status-publish","has-post-thumbnail","product_brand-national-instruments","product_cat-pxi-modules","first","instock","shipping-taxable","product-type-simple"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v25.0 (Yoast SEO v28.4) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>NI PXI-6651 PXI Synchronization Module 778725-01, In Stock | Project Pricing<\/title>\n<meta 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