{"id":34727,"date":"2026-08-07T15:51:55","date_gmt":"2026-08-07T07:51:55","guid":{"rendered":"https:\/\/pxisource.com\/?post_type=product&#038;p=34727"},"modified":"2026-08-31T12:40:43","modified_gmt":"2026-08-31T04:40:43","slug":"pxi-7952","status":"publish","type":"product","link":"https:\/\/pxisource.com\/ru\/product\/pxi-7952\/","title":{"rendered":"PXI-7952"},"content":{"rendered":"<h3>PXI-7952R Virtex-5 LX50 FlexRIO FPGA Module<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <strong>PXI-7952R<\/strong> is a National Instruments FlexRIO FPGA module designed for custom high-speed data acquisition, digital signal processing, protocol implementation and hardware-in-the-loop testing. It combines a user-programmable Xilinx Virtex-5 LX50 FPGA with 128 MB of onboard DRAM and an interface for interchangeable FlexRIO adapter modules.<\/p>\n<p>The module provides 132 general-purpose digital I\/O lines that can be configured as 132 single-ended channels, 66 differential pairs or a combination of both. Depending on the attached adapter module and FPGA implementation, the interface supports rates up to 400 Mb\/s per single-ended channel and 1 Gb\/s per LVDS differential pair.<\/p>\n<p>Unlike the PXI-7951R, the PXI-7952R includes two 64 MB DRAM banks for a total of 128 MB. This memory can buffer high-speed acquisition data, store generated waveforms and support FPGA applications in which the adapter-side data rate temporarily exceeds the available host-transfer bandwidth.<\/p>\n<h3>Key Features of the PXI-7952R<\/h3>\n<ul>\n<li>Xilinx Virtex-5 LX50 user-programmable FPGA<\/li>\n<li>7,200 FPGA slices<\/li>\n<li>28,800 lookup tables and flip-flops<\/li>\n<li>48 DSP48 processing slices<\/li>\n<li>1,728 kbits of embedded block RAM<\/li>\n<li>128 MB of onboard DRAM<\/li>\n<li>Two independent 64 MB DRAM banks<\/li>\n<li>Up to 800 MB\/s theoretical bandwidth per DRAM bank<\/li>\n<li>66 differential or 132 single-ended I\/O channels<\/li>\n<li>Up to 1 Gb\/s per LVDS differential pair<\/li>\n<li>Up to 400 Mb\/s per single-ended channel<\/li>\n<li>Three DMA channels for host communication<\/li>\n<li>40 MHz default FPGA timebase<\/li>\n<li>PXI_CLK10 and PXI trigger support<\/li>\n<li>Compatible with FlexRIO adapter modules<\/li>\n<li>Programmable with the LabVIEW FPGA Module<\/li>\n<\/ul>\n<h3>PXI-7952R Technical Specifications<\/h3>\n<table>\n<tbody>\n<tr>\n<th>Product Model<\/th>\n<td>PXI-7952R<\/td>\n<\/tr>\n<tr>\n<th>Part Number<\/th>\n<td>780561-01<\/td>\n<\/tr>\n<tr>\n<th>Product Type<\/th>\n<td>PXI FlexRIO FPGA module<\/td>\n<\/tr>\n<tr>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<td>Xilinx Virtex-5 LX50<\/td>\n<\/tr>\n<tr>\n<th>FPGA Slices<\/th>\n<td>7,200<\/td>\n<\/tr>\n<tr>\n<th>Lookup Tables and Flip-Flops<\/th>\n<td>28,800<\/td>\n<\/tr>\n<tr>\n<th>DSP Resources<\/th>\n<td>48 DSP48 slices with 25 \u00d7 18 multipliers<\/td>\n<\/tr>\n<tr>\n<th>Embedded Block RAM<\/th>\n<td>1,728 kbits<\/td>\n<\/tr>\n<tr>\n<th>Onboard DRAM<\/th>\n<td>128 MB total<\/td>\n<\/tr>\n<tr>\n<th>DRAM Configuration<\/th>\n<td>Two banks, 64 MB per bank<\/td>\n<\/tr>\n<tr>\n<th>DRAM Bandwidth<\/th>\n<td>Up to 800 MB\/s theoretical bandwidth per bank<\/td>\n<\/tr>\n<tr>\n<th>DRAM Access Width<\/th>\n<td>64 bits<\/td>\n<\/tr>\n<tr>\n<th>General-Purpose I\/O<\/th>\n<td>132 channels<\/td>\n<\/tr>\n<tr>\n<th>Differential I\/O<\/th>\n<td>66 pairs<\/td>\n<\/tr>\n<tr>\n<th>Maximum LVDS Data Rate<\/th>\n<td>Up to 1 Gb\/s per differential pair<\/td>\n<\/tr>\n<tr>\n<th>Maximum Single-Ended Data Rate<\/th>\n<td>Up to 400 Mb\/s per channel<\/td>\n<\/tr>\n<tr>\n<th>DMA Channels<\/th>\n<td>3<\/td>\n<\/tr>\n<tr>\n<th>Default FPGA Timebase<\/th>\n<td>40 MHz<\/td>\n<\/tr>\n<tr>\n<th>Reference Clock<\/th>\n<td>PXI_CLK10<\/td>\n<\/tr>\n<tr>\n<th>Timebase Accuracy<\/th>\n<td>\u00b1100 ppm<\/td>\n<\/tr>\n<tr>\n<th>Timebase Jitter<\/th>\n<td>250 ps peak-to-peak<\/td>\n<\/tr>\n<tr>\n<th>Trigger Resources<\/th>\n<td>PXI trigger lines and PXI star trigger<\/td>\n<\/tr>\n<tr>\n<th>\u0428\u0438\u043d\u043d\u044b\u0439 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441<\/th>\n<td>Conventional PXI<\/td>\n<\/tr>\n<tr>\n<th>Module Dimensions<\/th>\n<td>Approximately 18.8 \u00d7 12.9 cm (7.4 \u00d7 5.1 in.)<\/td>\n<\/tr>\n<tr>\n<th>Programming Environment<\/th>\n<td>LabVIEW FPGA with a compatible NI-RIO or FlexRIO driver<\/td>\n<\/tr>\n<tr>\n<th>Lifecycle Status<\/th>\n<td>Discontinued<\/td>\n<\/tr>\n<tr>\n<th>Recommended Replacement<\/th>\n<td>PXIe-7976R<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXI-7952R Part Number<\/h3>\n<table>\n<tbody>\n<tr>\n<th>Item<\/th>\n<th>Part Number<\/th>\n<th>\u041e\u043f\u0438\u0441\u0430\u043d\u0438\u0435<\/th>\n<\/tr>\n<tr>\n<td>PXI-7952R<\/td>\n<td>780561-01<\/td>\n<td>Virtex-5 LX50 FlexRIO FPGA module with 128 MB onboard DRAM<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>The PXI-7952R is an FPGA carrier rather than a complete fixed-function instrument. A compatible FlexRIO adapter module is normally required to provide external connectors, converters, transceivers and signal-conditioning circuitry. Verify the adapter model, driver version and required cables before ordering.<\/p>\n<h3>Virtex-5 LX50 FPGA Architecture<\/h3>\n<p>The PXI-7952R contains a Xilinx Virtex-5 LX50 FPGA that users can configure for application-specific processing and control. FPGA logic operates through dedicated parallel hardware resources, allowing several acquisition, generation, triggering and signal-processing operations to execute simultaneously.<\/p>\n<p>The FPGA provides 7,200 slices, 28,800 lookup tables and flip-flops, 48 DSP48 slices and 1,728 kbits of embedded block RAM. These resources can implement digital filters, triggers, counters, custom communication protocols, state machines and low-latency decision logic.<\/p>\n<p>The LX50 provides more programmable logic and DSP resources than the LX30 FPGA used by the PXI-7951R. This additional capacity supports larger applications while remaining compatible with the conventional PXI FlexRIO architecture.<\/p>\n<h3>128 MB Onboard DRAM<\/h3>\n<p>The PXI-7952R includes 128 MB of onboard DRAM divided into two independent 64 MB banks. Each bank provides theoretical bandwidth up to 800 MB\/s when accessed using an efficient FPGA memory architecture.<\/p>\n<p>Onboard DRAM can temporarily store acquired samples when the FlexRIO adapter produces data faster than the host can receive it. It can also contain waveform records, lookup tables, image frames and other large data sets that do not fit within embedded block RAM.<\/p>\n<p>The DRAM interface uses a 64-bit access size and is optimized for operation at 100 MHz. FPGA designs should use suitably sized data types and sequential memory access whenever practical to improve memory efficiency.<\/p>\n<h3>FlexRIO Adapter Module Interface<\/h3>\n<p>FlexRIO separates application-specific I\/O from the programmable FPGA carrier. The PXI-7952R supplies the FPGA, memory, timing and host interface, while the installed adapter module determines the physical connectors, number of channels, sample rate, voltage range and electrical signal standard.<\/p>\n<p>Compatible adapters can provide high-speed analog input, analog output, digital I\/O, RF conversion or specialized communication interfaces. This allows engineers to build a customized instrument around the requirements of a particular device or test system.<\/p>\n<p>The FPGA carrier and adapter module must be treated as a complete system. The capabilities of the PXI-7952R interface do not mean that every adapter exposes all 132 lines or supports the maximum theoretical I\/O rate.<\/p>\n<h3>66 Differential or 132 Single-Ended Channels<\/h3>\n<p>The adapter interface provides 132 general-purpose FPGA I\/O signals. They can be configured as 132 single-ended channels, 66 differential pairs or a mixture of single-ended and differential connections.<\/p>\n<p>Compatible differential interfaces can operate at rates up to 1 Gb\/s per LVDS pair. Single-ended channels support rates up to 400 Mb\/s, depending on FPGA timing, adapter circuitry, signal standard and external connection quality.<\/p>\n<p>High-speed operation requires controlled-impedance routing, suitable termination and careful clock alignment. Actual performance is determined by the complete signal path, including the adapter, connector, cable and test fixture.<\/p>\n<h3>Three DMA Channels<\/h3>\n<p>The PXI-7952R provides three DMA channels for transferring information between FPGA logic and the host controller. FPGA DMA FIFOs can support continuous acquisition, waveform generation, command transfer and status reporting without requiring the processor to handle every individual data value.<\/p>\n<p>Available host throughput depends on the PXI controller, chassis configuration, DMA block size and traffic from other modules. The conventional PXI interface has lower transfer capacity than later PXI Express FlexRIO modules, so high-data-rate applications should use FPGA processing and onboard buffering efficiently.<\/p>\n<h3>FPGA-Based Signal Processing<\/h3>\n<p>The 48 DSP48 slices provide hardware multipliers and accumulation resources for real-time mathematical operations. They can be used for finite impulse response filters, decimation, scaling, mixing, control algorithms and signal analysis.<\/p>\n<p>Processing information directly on the FPGA can reduce latency and decrease host-transfer requirements. Instead of transferring every acquired sample, the FPGA can send calculated values, selected events or reduced data sets to the controller.<\/p>\n<h3>Deterministic Hardware Timing<\/h3>\n<p>The FPGA executes operations according to compiled hardware timing rather than a nondeterministic desktop operating system. This allows the PXI-7952R to generate repeatable triggers, control digital protocols and react to external events with predictable latency.<\/p>\n<p>The default FPGA timebase is 40 MHz. PXI_CLK10, PXI trigger lines and the PXI star trigger can help coordinate the module with other instruments installed in the same PXI system.<\/p>\n<h3>Buffered High-Speed Acquisition<\/h3>\n<p>When paired with a suitable digitizer adapter, the PXI-7952R can acquire high-speed analog or digital data and store it in onboard DRAM. The FPGA can add triggering, preprocessing and record-management logic before transferring the results to the host.<\/p>\n<p>Buffered acquisition is useful for bursts, transient signals and triggered records that cannot be streamed continuously over the PXI bus at the full adapter sample rate.<\/p>\n<h3>Waveform Generation<\/h3>\n<p>Onboard DRAM can hold digital or analog waveform records for repeated output through a compatible adapter module. The FPGA can control waveform timing, triggering, sequencing and conditional generation.<\/p>\n<p>Generation accuracy, sample rate and voltage performance depend on the installed adapter. The FPGA design must coordinate DRAM access with the adapter clock to prevent underflow during high-speed output.<\/p>\n<h3>Custom Digital Protocols<\/h3>\n<p>The PXI-7952R can implement custom and proprietary digital protocols directly in FPGA hardware. Developers can define clocking, framing, encoding, checksums, handshaking and error-insertion behavior according to the device under test.<\/p>\n<p>This capability is useful when a standard communication instrument does not support the required protocol or when deterministic bit-level control is needed.<\/p>\n<h3>Hardware-in-the-Loop Testing<\/h3>\n<p>The module can provide deterministic stimulus generation and response monitoring in hardware-in-the-loop systems. FPGA logic can emulate sensors, decode controller outputs and apply conditional responses without waiting for a host-software loop.<\/p>\n<p>The attached adapter and external interface must provide the required voltage levels, isolation and protection. Confirm the electrical limits of the complete test system before connecting automotive, aerospace or industrial controllers.<\/p>\n<h3>Image and Sensor Processing<\/h3>\n<p>When paired with a compatible camera or high-speed digital adapter, the PXI-7952R can perform pixel-level processing, threshold detection, data formatting and region-based calculations. Onboard DRAM can temporarily store frames or line data.<\/p>\n<p>The capacity of the Virtex-5 LX50 FPGA should be evaluated against the required image dimensions, bit depth, processing algorithm and frame rate. More advanced algorithms may require a larger FPGA module.<\/p>\n<h3>Custom FlexRIO Adapter Development<\/h3>\n<p>Developers can pair the PXI-7952R with a custom FlexRIO adapter module containing specialized converters, connectors and interface circuitry. This provides a path for creating application-specific FPGA instruments.<\/p>\n<p>Custom adapter design requires attention to FPGA pin assignments, clock distribution, power consumption, signal integrity and the FlexRIO mechanical interface. The relevant FlexRIO Adapter Module Development Kit requirements should be followed.<\/p>\n<h3>LabVIEW FPGA Programming<\/h3>\n<p>The PXI-7952R is programmed using the LabVIEW FPGA Module with a compatible NI-RIO or FlexRIO driver. The FPGA application is compiled into a bitfile that executes directly on the Virtex-5 device.<\/p>\n<p>A host application can read and write FPGA controls, communicate through DMA FIFOs, respond to interrupts and monitor application status. Existing systems should preserve compatible development software and compiled bitfiles because current software releases may not support every discontinued FlexRIO product.<\/p>\n<h3>Typical PXI-7952R Applications<\/h3>\n<ul>\n<li>High-speed analog and digital data acquisition<\/li>\n<li>Buffered waveform capture<\/li>\n<li>Custom digital protocol implementation<\/li>\n<li>Real-time digital signal processing<\/li>\n<li>\u0421\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u044f \u0441 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u043c \u0432\u0445\u043e\u0434\u043e\u043c<\/li>\n<li>Bit-error-rate testing<\/li>\n<li>High-speed pattern generation<\/li>\n<li>Inline filtering and event detection<\/li>\n<li>Image and sensor processing<\/li>\n<li>Communications research<\/li>\n<li>Production functional testing<\/li>\n<li>Custom instrumentation development<\/li>\n<\/ul>\n<h3>PXI-7952R Troubleshooting<\/h3>\n<h4>The Module Is Not Detected<\/h4>\n<p>Confirm that the PXI-7952R is fully installed in a compatible PXI or PXI hybrid slot. Check chassis power, controller communication and installation of a driver version that supports the module. Inspect the system in NI Measurement &amp; Automation Explorer.<\/p>\n<h4>The FPGA Bitfile Does Not Load<\/h4>\n<p>Verify that the bitfile was compiled specifically for the PXI-7952R and the installed adapter module. Bitfiles created for another FPGA target can contain incompatible resources and pin assignments.<\/p>\n<h4>The FPGA Design Does Not Compile<\/h4>\n<p>Review logic, DSP, block-RAM and timing utilization. Reduce parallel operations, reuse arithmetic resources or move noncritical processing to the host if the design exceeds the Virtex-5 LX50 capacity.<\/p>\n<h4>DRAM Data Is Corrupted<\/h4>\n<p>Confirm that the memory address remains within the allocated range and that read and write operations use the correct data width. Coordinate simultaneous access carefully and verify that the FPGA waits for each DRAM operation to complete.<\/p>\n<h4>DRAM Throughput Is Lower Than Expected<\/h4>\n<p>Use sequential memory access, appropriate burst sizes and a 64-bit data type when practical. Small or irregular transactions can reduce efficiency and prevent the design from approaching the theoretical bandwidth.<\/p>\n<h4>DMA FIFO Overflow Occurs<\/h4>\n<p>Increase the FIFO allocation, transfer data in larger host blocks or reduce the FPGA production rate. Filtering, decimation and event selection can reduce the amount of information transferred across the PXI bus.<\/p>\n<h4>Waveform Generation Underflows<\/h4>\n<p>Preload sufficient waveform data into DRAM and ensure that the FPGA retrieves it before the adapter requires the next sample. Review memory arbitration, clock-domain crossings and host refill timing.<\/p>\n<h4>A High-Speed Interface Produces Errors<\/h4>\n<p>Check signal termination, impedance, cable length, clock alignment and FPGA timing closure. Confirm that the adapter and external fixture support the selected I\/O standard and requested data rate.<\/p>\n<h4>The Adapter Module Is Not Recognized<\/h4>\n<p>Verify that the adapter is compatible with the PXI-7952R and correctly identified in the LabVIEW FPGA project. Power down the chassis before reseating the adapter and inspect its card-edge connector for damage.<\/p>\n<h3>PXI-7952R Comparison with Similar FlexRIO FPGA Modules<\/h3>\n<table>\n<tbody>\n<tr>\n<th>\u041c\u043e\u0434\u0435\u043b\u044c<\/th>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<th>FPGA Resources<\/th>\n<th>Onboard DRAM<\/th>\n<th>Best Suited For<\/th>\n<\/tr>\n<tr>\n<td>PXI-7951R<\/td>\n<td>Virtex-5 LX30<\/td>\n<td>4,800 slices, 32 DSP48, 1,152 kbits BRAM<\/td>\n<td>\u041d\u0438\u0447\u0435\u0433\u043e<\/td>\n<td>Moderate FPGA applications without large buffers<\/td>\n<\/tr>\n<tr>\n<td>PXI-7952R<\/td>\n<td>Virtex-5 LX50<\/td>\n<td>7,200 slices, 48 DSP48, 1,728 kbits BRAM<\/td>\n<td>128 MB<\/td>\n<td>Buffered acquisition and mid-size FPGA designs<\/td>\n<\/tr>\n<tr>\n<td>PXI-7953R<\/td>\n<td>Virtex-5 LX85<\/td>\n<td>12,960 slices, 48 DSP48, 3,456 kbits BRAM<\/td>\n<td>128 MB<\/td>\n<td>Larger parallel-processing applications<\/td>\n<\/tr>\n<tr>\n<td>PXI-7954R<\/td>\n<td>Virtex-5 LX110<\/td>\n<td>17,280 slices, 64 DSP48, 4,608 kbits BRAM<\/td>\n<td>128 MB<\/td>\n<td>Largest FPGA designs in the PXI-795xR family<\/td>\n<\/tr>\n<tr>\n<td>PXIe-7976R<\/td>\n<td>Kintex-7 410T<\/td>\n<td>63,550 slices, 1,540 DSP48, 28,620 kbits BRAM<\/td>\n<td>2 GB<\/td>\n<td>Modern high-throughput FlexRIO systems<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXI-7952R vs PXI-7951R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7951\/\">PXI-7951R<\/a> uses a smaller Virtex-5 LX30 FPGA and does not include onboard DRAM. The PXI-7952R provides a larger LX50 FPGA and 128 MB of DRAM.<\/p>\n<p>Choose the PXI-7951R for smaller FPGA designs that can operate using block RAM or continuous host streaming. Choose the PXI-7952R when the application requires additional processing resources or local data buffering.<\/p>\n<h3>PXI-7952R vs PXI-7953R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7953\/\">PXI-7953R<\/a> uses a larger Virtex-5 LX85 FPGA with 12,960 slices and 3,456 kbits of embedded block RAM. Both models include 128 MB of onboard DRAM.<\/p>\n<p>Select the PXI-7952R for moderate FPGA applications that fit within the LX50. Choose the PXI-7953R when additional parallel logic and embedded memory are required.<\/p>\n<h3>PXI-7952R vs PXI-7954R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/%d0%bf%d1%85%d0%b8-7954\/\">PXI-7954R<\/a> provides the largest FPGA in the conventional PXI-795xR family. Its Virtex-5 LX110 contains 17,280 slices, 64 DSP48 resources and 4,608 kbits of embedded block RAM.<\/p>\n<p>The PXI-7952R can be more economical for established designs that do not require the additional LX110 capacity. Both modules provide 128 MB of onboard DRAM.<\/p>\n<h3>PXI-7952R vs PXIe-7976R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7976\/\">PXIe-7976R<\/a> is NI\u2019s recommended replacement for the discontinued PXI-7952R. It uses a Kintex-7 410T FPGA, includes 2 GB of DRAM and provides substantially greater FPGA and host-transfer performance.<\/p>\n<p>The PXIe-7976R requires a compatible PXI Express slot and a supported software environment. Existing FPGA code must be recompiled and may require modification because the replacement uses a different FPGA architecture and host interface.<\/p>\n<h3>Recommended Related Products<\/h3>\n<ul>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7951\/\">PXI-7951R Virtex-5 LX30 FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7953\/\">PXI-7953R Virtex-5 LX85 FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/%d0%bf%d1%85%d0%b8-7954\/\">PXI-7954R Virtex-5 LX110 FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7962\/\">PXIe-7962R Virtex-5 SX50T FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7976\/\">PXIe-7976R Kintex-7 FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/ni-6581b\/\">NI-6581B High-Speed Digital FlexRIO Adapter Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product-category\/%d0%bd%d0%b8\/pxi-%d1%81%d0%b8%d1%81%d1%82%d0%b5%d0%bc%d1%81\/%d0%bc%d0%be%d0%b4%d1%83%d0%bb%d0%b8-pxi\/\">View More NI PXI and PXI Express Modules<\/a><\/li>\n<\/ul>\n<h3>Selecting the Right FlexRIO FPGA Module<\/h3>\n<p>Choose the PXI-7952R when maintaining a conventional PXI FlexRIO system that requires a Virtex-5 LX50 FPGA and 128 MB of onboard buffering. It provides a practical balance of logic resources, DRAM capacity and adapter-module flexibility.<\/p>\n<p>Select the PXI-7953R or PXI-7954R when the FPGA design requires additional logic and embedded block RAM. For a new system requiring significantly higher processing capacity, larger memory and faster host transfer, consider the PXIe-7976R.<\/p>\n<h3>Why Choose the PXI-7952R?<\/h3>\n<ul>\n<li>Maintains compatibility with validated Virtex-5 FlexRIO systems<\/li>\n<li>Provides a user-programmable LX50 FPGA<\/li>\n<li>Includes 128 MB of onboard DRAM<\/li>\n<li>Supports buffered acquisition and waveform generation<\/li>\n<li>Provides 66 differential or 132 single-ended I\/O signals<\/li>\n<li>Supports LVDS rates up to 1 Gb\/s per pair<\/li>\n<li>Provides three DMA channels for host communication<\/li>\n<li>Supports deterministic processing and custom protocols<\/li>\n<li>Works with compatible interchangeable FlexRIO adapters<\/li>\n<li>Integrates with LabVIEW FPGA and NI-RIO software<\/li>\n<\/ul>\n<h3>Frequently Asked Questions<\/h3>\n<h4>What Is the PXI-7952R?<\/h4>\n<p>The PXI-7952R is a conventional PXI FlexRIO FPGA module featuring a Xilinx Virtex-5 LX50 FPGA, 128 MB of onboard DRAM and an interface for compatible FlexRIO adapter modules.<\/p>\n<h4>What Is the PXI-7952R Part Number?<\/h4>\n<p>The standard NI part number for the PXI-7952R is <strong>780561-01<\/strong>.<\/p>\n<h4>How Much DRAM Does the PXI-7952R Provide?<\/h4>\n<p>The module provides 128 MB of onboard DRAM divided into two independent 64 MB banks.<\/p>\n<h4>What FPGA Is Used in the PXI-7952R?<\/h4>\n<p>The PXI-7952R uses a Xilinx Virtex-5 LX50 FPGA with 7,200 slices, 48 DSP48 resources and 1,728 kbits of embedded block RAM.<\/p>\n<h4>How Many Digital I\/O Lines Are Available?<\/h4>\n<p>The adapter interface supports 132 single-ended channels, 66 differential pairs or a combination of both. Actual external I\/O depends on the installed FlexRIO adapter module.<\/p>\n<h4>What Is the Maximum Differential Data Rate?<\/h4>\n<p>The interface supports rates up to 1 Gb\/s per LVDS differential pair when used with compatible hardware and a suitable FPGA design.<\/p>\n<h4>How Many DMA Channels Does It Have?<\/h4>\n<p>The PXI-7952R provides three DMA channels for transferring data between the FPGA and host controller.<\/p>\n<h4>Does the PXI-7952R Require an Adapter Module?<\/h4>\n<p>A compatible FlexRIO adapter module is normally required to provide external connectors and application-specific analog, digital or RF I\/O circuitry.<\/p>\n<h4>Which Software Programs the PXI-7952R?<\/h4>\n<p>The FPGA is programmed using a compatible version of the LabVIEW FPGA Module and NI-RIO or FlexRIO software. Legacy software compatibility should be confirmed before purchase.<\/p>\n<h4>Is the PXI-7952R Still Manufactured?<\/h4>\n<p>No. The PXI-7952R has been discontinued. Units may still be available from refurbished, surplus or previously owned inventory.<\/p>\n<h4>What Is the Recommended Replacement?<\/h4>\n<p>NI identifies the PXIe-7976R as the recommended replacement. Migration requires evaluation of the PXI Express chassis, software environment, adapter module and existing FPGA code.<\/p>\n<h3>Request a Quote for the PXI-7952R<\/h3>\n<p>Contact us for current availability, condition, lead time and project pricing for the <strong>PXI-7952R Virtex-5 LX50 FlexRIO FPGA Module<\/strong>. We can also help identify compatible FlexRIO adapter modules, PXI chassis and migration options for discontinued FPGA-based test systems.<\/p>","protected":false},"excerpt":{"rendered":"<p>PXI-7952R Virtex-5 LX50 FlexRIO FPGA Module The PXI-7952R is a National Instruments FlexRIO FPGA module designed for custom high-speed data<\/p>","protected":false},"featured_media":31288,"template":"","meta":{"_acf_changed":false},"product_brand":[18],"product_cat":[667],"product_tag":[],"class_list":["post-34727","product","type-product","status-publish","has-post-thumbnail","product_brand-national-instruments","product_cat-pxi-modules","first","instock","shipping-taxable","product-type-simple"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v25.0 (Yoast SEO v28.4) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>NI PXI-7952 PXI Multifunction I\/O Module 780561-01, In Stock | Project Pricing<\/title>\n<meta name=\"description\" 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