{"id":32482,"date":"2026-04-30T16:13:26","date_gmt":"2026-04-30T08:13:26","guid":{"rendered":"https:\/\/pxisource.com\/?post_type=product&#038;p=32482"},"modified":"2026-08-29T12:27:12","modified_gmt":"2026-08-29T04:27:12","slug":"pxi-7851","status":"publish","type":"product","link":"https:\/\/pxisource.com\/ru\/product\/pxi-7851\/","title":{"rendered":"PXI-7851"},"content":{"rendered":"<h3>PXI-7851 Multifunction Reconfigurable I\/O Module<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <strong>PXI-7851<\/strong>, also known as the PXI-7851R, is a multifunction reconfigurable I\/O module featuring a user-programmable Xilinx Virtex-5 LX30 FPGA. It combines analog input, analog output and digital I\/O resources with direct FPGA control for deterministic measurement and control applications.<\/p>\n<p>The module provides eight 16-bit analog inputs with independent sampling rates up to 750 kS\/s per channel, eight 16-bit analog outputs at up to 1 MS\/s per channel and 96 bidirectional digital I\/O lines.<\/p>\n<h3>Key Features of the PXI-7851<\/h3>\n<ul>\n<li>Xilinx Virtex-5 LX30 user-programmable FPGA<\/li>\n<li>Eight 16-bit analog input channels<\/li>\n<li>750 kS\/s maximum sampling rate per analog input<\/li>\n<li>Dedicated ADC for every analog input channel<\/li>\n<li>Eight 16-bit analog output channels<\/li>\n<li>1 MS\/s maximum update rate per analog output<\/li>\n<li>\u00b110 V analog input and output ranges<\/li>\n<li>96 bidirectional TTL digital I\/O lines<\/li>\n<li>Programmable digital power-on states<\/li>\n<li>Independent channel timing and triggering<\/li>\n<li>Support for multirate analog acquisition<\/li>\n<li>Three 68-pin VHDCI I\/O connectors<\/li>\n<li>PXI Hybrid bus interface<\/li>\n<li>Programmable with the LabVIEW FPGA Module<\/li>\n<\/ul>\n<h3>PXI-7851 Technical Specifications<\/h3>\n<table>\n<tbody>\n<tr>\n<th>Product Model<\/th>\n<td>PXI-7851 \/ PXI-7851R<\/td>\n<\/tr>\n<tr>\n<th>Part Number<\/th>\n<td>780339-01<\/td>\n<\/tr>\n<tr>\n<th>Product Type<\/th>\n<td>Multifunction Reconfigurable I\/O Module<\/td>\n<\/tr>\n<tr>\n<th>Product Family<\/th>\n<td>NI R Series Multifunction RIO<\/td>\n<\/tr>\n<tr>\n<th>\u0428\u0438\u043d\u043d\u044b\u0439 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441<\/th>\n<td>PXI Hybrid<\/td>\n<\/tr>\n<tr>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<td>Xilinx Virtex-5 LX30<\/td>\n<\/tr>\n<tr>\n<th>FPGA Flip-Flops<\/th>\n<td>19,200<\/td>\n<\/tr>\n<tr>\n<th>FPGA 6-Input LUTs<\/th>\n<td>19,200<\/td>\n<\/tr>\n<tr>\n<th>DSP48 Slices<\/th>\n<td>32<\/td>\n<\/tr>\n<tr>\n<th>Embedded Block RAM<\/th>\n<td>1,152 kbits<\/td>\n<\/tr>\n<tr>\n<th>Analog Input Channels<\/th>\n<td>8<\/td>\n<\/tr>\n<tr>\n<th>Analog Input Resolution<\/th>\n<td>16 bits<\/td>\n<\/tr>\n<tr>\n<th>Maximum Analog Input Rate<\/th>\n<td>750 kS\/s per channel<\/td>\n<\/tr>\n<tr>\n<th>Analog Input Range<\/th>\n<td>\u00b110 V<\/td>\n<\/tr>\n<tr>\n<th>Input Modes<\/th>\n<td>Differential, RSE or NRSE<\/td>\n<\/tr>\n<tr>\n<th>Analog Output Channels<\/th>\n<td>8<\/td>\n<\/tr>\n<tr>\n<th>Analog Output Resolution<\/th>\n<td>16 bits<\/td>\n<\/tr>\n<tr>\n<th>Maximum Analog Output Rate<\/th>\n<td>1 \u041c\u0432\u044b\u0431\/\u0441 \u043d\u0430 \u043a\u0430\u043d\u0430\u043b<\/td>\n<\/tr>\n<tr>\n<th>Analog Output Range<\/th>\n<td>\u00b110 V<\/td>\n<\/tr>\n<tr>\n<th>Digital I\/O Channels<\/th>\n<td>96 bidirectional lines<\/td>\n<\/tr>\n<tr>\n<th>Digital Compatibility<\/th>\n<td>TTL, 3.3 V output and 5 V input compatible<\/td>\n<\/tr>\n<tr>\n<th>Digital Output Current<\/th>\n<td>4 mA source or sink<\/td>\n<\/tr>\n<tr>\n<th>Maximum Clock Rate<\/th>\n<td>40 MHz base clock<\/td>\n<\/tr>\n<tr>\n<th>Onboard DRAM<\/th>\n<td>\u041d\u0438\u0447\u0435\u0433\u043e<\/td>\n<\/tr>\n<tr>\n<th>I\/O Connectors<\/th>\n<td>3 \u00d7 68-pin female VHDCI<\/td>\n<\/tr>\n<tr>\n<th>Operating Temperature<\/th>\n<td>0\u00b0C to 55\u00b0C<\/td>\n<\/tr>\n<tr>\n<th>Dimensions<\/th>\n<td>16 \u00d7 10 cm, standard 3U PXI module<\/td>\n<\/tr>\n<tr>\n<th>Weight<\/th>\n<td>Approximately 152 g<\/td>\n<\/tr>\n<tr>\n<th>Product Status<\/th>\n<td>Mature; not recommended for new designs<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXI-7851 Part Number and Configuration<\/h3>\n<table>\n<tbody>\n<tr>\n<th>\u041c\u043e\u0434\u0435\u043b\u044c<\/th>\n<th>Part Number<\/th>\n<th>\u041a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f<\/th>\n<\/tr>\n<tr>\n<td>PXI-7851<\/td>\n<td>780339-01<\/td>\n<td>Virtex-5 LX30 FPGA, 8 AI, 8 AO and 96 digital I\/O<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>User-Programmable Virtex-5 FPGA<\/h3>\n<p>The PXI-7851 uses a Xilinx Virtex-5 LX30 FPGA that can be programmed with the LabVIEW FPGA Module. Custom FPGA logic can directly control I\/O timing, triggering, signal processing and communication protocols without relying on nondeterministic host-computer timing.<\/p>\n<p>The FPGA includes 19,200 flip-flops, 19,200 six-input lookup tables, 32 DSP48 slices and 1,152 kbits of embedded block RAM. These resources support custom control loops, digital filtering, mathematical processing and protocol logic.<\/p>\n<h3>Eight Independent Analog Inputs<\/h3>\n<p>The PXI-7851 provides eight 16-bit analog input channels with a \u00b110 V range. Each channel has a dedicated successive-approximation ADC capable of sampling at up to 750 kS\/s.<\/p>\n<p>Because the channels do not share a multiplexed ADC, each input can use independent timing and triggering. This design supports simultaneous acquisition, individual channel triggers and multirate sampling that conventional multifunction DAQ devices may not provide.<\/p>\n<h3>Analog Input Connection Modes<\/h3>\n<p>The analog input channels support differential, referenced single-ended and nonreferenced single-ended connection modes. The selected input mode applies to all analog input channels.<\/p>\n<ul>\n<li><strong>Differential:<\/strong> Provides improved noise rejection for floating or low-level signals.<\/li>\n<li><strong>RSE:<\/strong> References input signals to the device analog ground.<\/li>\n<li><strong>NRSE:<\/strong> References input signals to a shared remote-sense connection.<\/li>\n<\/ul>\n<p>The appropriate wiring configuration depends on signal grounding, source impedance, cable length and the electrical noise present in the test system.<\/p>\n<h3>Eight Analog Outputs<\/h3>\n<p>The PXI-7851 provides eight single-ended, 16-bit voltage outputs with a \u00b110 V range. Each channel supports update rates up to 1 MS\/s and can be controlled directly from the FPGA.<\/p>\n<p>These outputs can generate control signals, simulate sensors, provide actuator commands and produce custom waveforms. The power-on output state can be configured according to the safety requirements of the application.<\/p>\n<h3>96 Bidirectional Digital I\/O Lines<\/h3>\n<p>The module includes 96 TTL-compatible digital I\/O lines. Direction and power-on state can be configured by line, allowing the digital resources to implement custom interfaces, timing signals, triggers and control functions.<\/p>\n<p>Digital outputs operate at 3.3 V logic levels, while inputs can accept compatible signals up to 5.5 V. Each line can source or sink up to 4 mA within the device specifications.<\/p>\n<h3>Deterministic Timing and Control<\/h3>\n<p>FPGA-based execution provides hardware-timed response without interruption from a desktop operating system. Control algorithms, safety interlocks and custom triggers can execute directly on the module with predictable timing.<\/p>\n<p>The PXI-7851 is especially useful when standard DAQ timing engines cannot provide the required channel independence, control-loop speed or custom digital behavior.<\/p>\n<h3>Typical PXI-7851 Applications<\/h3>\n<ul>\n<li>\u0421\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u044f \u0441 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u043c \u0432\u0445\u043e\u0434\u043e\u043c<\/li>\n<li>High-speed closed-loop control<\/li>\n<li>Custom digital protocol implementation<\/li>\n<li>Sensor and actuator simulation<\/li>\n<li>Automotive electronic control unit testing<\/li>\n<li>Aerospace system validation<\/li>\n<li>Power electronics testing<\/li>\n<li>\u041c\u043e\u043d\u0438\u0442\u043e\u0440\u0438\u043d\u0433 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u044f \u043e\u0431\u043e\u0440\u0443\u0434\u043e\u0432\u0430\u043d\u0438\u044f<\/li>\n<li>Custom data acquisition systems<\/li>\n<li>Research and rapid control prototyping<\/li>\n<li>Electronic device functional testing<\/li>\n<\/ul>\n<h3>LabVIEW FPGA Programming<\/h3>\n<p>The PXI-7851 is programmed using the LabVIEW FPGA Module and a compatible R Series driver. Engineers can create custom hardware personalities for analog acquisition, waveform generation, digital communication and deterministic control.<\/p>\n<p>A host application can communicate with the compiled FPGA personality to configure tests, transfer data and display results. Because FPGA compilation can require substantial time, the I\/O architecture and resource allocation should be planned before beginning a large application.<\/p>\n<h3>Multirate Sampling and Individual Triggering<\/h3>\n<p>Dedicated ADCs allow different analog input channels to operate at different effective rates. Engineers can acquire faster-changing signals at higher rates while sampling slower sensor signals less frequently.<\/p>\n<p>Trigger logic can also be implemented independently for individual channels. This provides more flexibility than conventional multiplexed DAQ devices that share one conversion clock and trigger configuration across several inputs.<\/p>\n<h3>VHDCI Connectivity and Accessories<\/h3>\n<p>The PXI-7851 provides three 68-pin female high-density VHDCI connectors. Compatible shielded cables and connector blocks are required to access the analog and digital signals.<\/p>\n<p>NI SCB-68 or SCB-68A connector blocks may be used with the correct R Series pinout labels and compatible cables. The pinout differs from conventional DAQ devices, so the PXI-7851 wiring diagram must be verified before connecting signals.<\/p>\n<p>The NI-9151 R Series expansion chassis can connect to compatible digital connectors and add signal-conditioned C Series I\/O modules. One PXI-7851 can support up to two compatible NI-9151 expansion chassis.<\/p>\n<h3>PXI Chassis Integration<\/h3>\n<p>The PXI-7851 installs in a compatible PXI or PXI Hybrid chassis. It can be synchronized with other PXI instruments through chassis timing and triggering resources.<\/p>\n<p>The module does not include onboard DRAM. Applications requiring high-volume data buffering should consider FPGA block RAM limits, DMA transfers and host-controller performance during system design.<\/p>\n<h3>PXI-7851 Troubleshooting<\/h3>\n<h4>The module is not detected in NI MAX<\/h4>\n<p>Confirm that the PXI-7851 is fully seated in a compatible PXI or PXI Hybrid slot. Verify the chassis, controller, R Series driver and LabVIEW FPGA support, then refresh the device list in NI Measurement &amp; Automation Explorer.<\/p>\n<h4>The FPGA VI will not compile<\/h4>\n<p>Check that the installed LabVIEW FPGA version supports the PXI-7851 and its Virtex-5 compilation tools. Review FPGA resource usage if the design exceeds the available LUT, register, DSP or block RAM capacity.<\/p>\n<h4>Analog input readings are noisy<\/h4>\n<p>Select the appropriate differential or single-ended input mode, use shielded cables and review grounding. Keep analog wiring away from switching power supplies, motors and high-current digital lines.<\/p>\n<h4>Analog input channels do not sample at the expected rate<\/h4>\n<p>Verify that each FPGA I\/O node and loop are configured for the intended timing. Account for FPGA processing, DMA transfer and host-reading requirements when calculating sustained acquisition rates.<\/p>\n<h4>Digital signals are not recognized correctly<\/h4>\n<p>Confirm the external logic voltage, grounding and input thresholds. The outputs use 3.3 V logic, while the inputs are compatible with supported 3.3 V and 5 V TTL signals.<\/p>\n<h4>The connector-block signals do not match the FPGA channels<\/h4>\n<p>Use the PXI-7851-specific VHDCI connector pinout. Do not assume that a standard DAQ device or another R Series model uses the same connector-block channel mapping.<\/p>\n<h3>PXI-7851 Compared with Related R Series Modules<\/h3>\n<table>\n<tbody>\n<tr>\n<th>\u041c\u043e\u0434\u0435\u043b\u044c<\/th>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<th>Analog Input Rate<\/th>\n<th>I\/O Configuration<\/th>\n<th>Best Suited For<\/th>\n<\/tr>\n<tr>\n<td>PXI-7851<\/td>\n<td>Virtex-5 LX30<\/td>\n<td>750 kS\/s<\/td>\n<td>8 AI, 8 AO, 96 DIO<\/td>\n<td>FPGA-based multifunction control<\/td>\n<\/tr>\n<tr>\n<td>\u041f\u0425\u0418-7841<\/td>\n<td>Virtex-5 LX30<\/td>\n<td>200 kS\/s<\/td>\n<td>8 AI, 8 AO, 96 DIO<\/td>\n<td>Lower-speed multifunction FPGA applications<\/td>\n<\/tr>\n<tr>\n<td>PXI-7852<\/td>\n<td>Virtex-5 LX50<\/td>\n<td>750 kS\/s<\/td>\n<td>8 AI, 8 AO, 96 DIO<\/td>\n<td>Applications requiring more FPGA resources<\/td>\n<\/tr>\n<tr>\n<td>PXI-7853<\/td>\n<td>Virtex-5 LX85<\/td>\n<td>750 kS\/s<\/td>\n<td>8 AI, 8 AO, 96 DIO<\/td>\n<td>Larger FPGA processing designs<\/td>\n<\/tr>\n<tr>\n<td>PXI-7854<\/td>\n<td>Virtex-5 LX110<\/td>\n<td>750 kS\/s<\/td>\n<td>8 AI, 8 AO, 96 DIO<\/td>\n<td>Maximum FPGA capacity in the legacy family<\/td>\n<\/tr>\n<tr>\n<td>PXIe-7847<\/td>\n<td>Kintex-7<\/td>\n<td>Higher-performance generation<\/td>\n<td>Multifunction analog and digital I\/O<\/td>\n<td>Newer PXI Express FPGA systems<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Recommended Related Products<\/h3>\n<ul>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7841\/\">PXI-7841 Multifunction RIO Module<\/a> \u2013 A lower-speed Virtex-5 LX30 alternative with a similar I\/O configuration.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7852\/\">PXI-7852 Multifunction RIO Module<\/a> \u2013 A 750 kS\/s module with a larger Virtex-5 LX50 FPGA.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7853\/\">PXI-7853 Multifunction RIO Module<\/a> \u2013 A Virtex-5 LX85 model for applications requiring additional FPGA resources.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxi-7854\/\">PXI-7854 Multifunction RIO Module<\/a> \u2013 A Virtex-5 LX110 version for larger FPGA designs.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7847\/\">PXIe-7847 Multifunction Reconfigurable I\/O Module<\/a> \u2013 A newer Kintex-7-based PXI Express alternative.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-1092\/\">PXIe-1092 PXI Express Chassis<\/a> \u2013 A modular chassis for synchronized measurement and control systems.<\/li>\n<\/ul>\n<p>Additional FPGA, data acquisition and control products are available in the <a href=\"https:\/\/pxisource.com\/ru\/product-category\/%d0%bd%d0%b8\/pxi-%d1%81%d0%b8%d1%81%d1%82%d0%b5%d0%bc%d1%81\/%d0%bc%d0%be%d0%b4%d1%83%d0%bb%d0%b8-pxi\/\">NI PXI Modules<\/a> category.<\/p>\n<h3>Selecting the PXI-7851<\/h3>\n<p>Choose the PXI-7851 when maintaining or expanding a system that requires eight 750 kS\/s analog inputs, eight high-speed analog outputs, 96 digital lines and direct Virtex-5 FPGA control.<\/p>\n<p>The PXI-7851 has mature product status and is not recommended for new system designs. For a new application, compare current Kintex-7 R Series PXI Express modules according to required analog performance, digital I\/O voltage and FPGA capacity.<\/p>\n<h3>Why Choose the PXI-7851?<\/h3>\n<ul>\n<li>Combines analog input, analog output and digital I\/O<\/li>\n<li>Provides a dedicated ADC for every analog input<\/li>\n<li>Supports deterministic FPGA-based processing<\/li>\n<li>Allows custom timing, triggering and protocols<\/li>\n<li>Supports multirate sampling and independent channel triggers<\/li>\n<li>Provides 96 configurable digital I\/O lines<\/li>\n<li>Integrates with existing PXI R Series systems<\/li>\n<\/ul>\n<h3>Frequently Asked Questions<\/h3>\n<h4>What is the PXI-7851 used for?<\/h4>\n<p>The PXI-7851 is used for FPGA-based data acquisition, hardware-in-the-loop testing, custom digital protocols, sensor simulation and deterministic control.<\/p>\n<h4>How many analog channels does the PXI-7851 provide?<\/h4>\n<p>It provides eight 16-bit analog inputs and eight 16-bit analog outputs.<\/p>\n<h4>What is the maximum analog input sampling rate?<\/h4>\n<p>Each analog input channel can sample at rates up to 750 kS\/s using its dedicated ADC.<\/p>\n<h4>What is the analog output update rate?<\/h4>\n<p>Each analog output supports update rates up to 1 MS\/s with 16-bit resolution.<\/p>\n<h4>How many digital I\/O lines are available?<\/h4>\n<p>The PXI-7851 provides 96 bidirectional TTL-compatible digital I\/O lines.<\/p>\n<h4>Which FPGA does the PXI-7851 use?<\/h4>\n<p>The module uses a Xilinx Virtex-5 LX30 FPGA with 19,200 flip-flops, 32 DSP48 slices and 1,152 kbits of embedded block RAM.<\/p>\n<h4>Does the PXI-7851 have onboard DRAM?<\/h4>\n<p>No. The PXI-7851 does not include onboard DRAM. It uses FPGA block RAM and DMA communication with the host system.<\/p>\n<h4>What software is required?<\/h4>\n<p>FPGA customization requires a compatible version of LabVIEW FPGA and the supported NI R Series driver. A host application is typically created in LabVIEW or another supported environment.<\/p>\n<h4>What is the part number for the PXI-7851?<\/h4>\n<p>The standard NI part number for the PXI-7851 is <strong>780339-01<\/strong>.<\/p>\n<h3>Request a Quote for the PXI-7851<\/h3>\n<p>Contact us for current availability, condition, lead time and project pricing for the <strong>PXI-7851 Multifunction Reconfigurable I\/O Module<\/strong>. We can also help identify compatible VHDCI cables, connector blocks, PXI chassis and newer R Series replacement options.<\/p>","protected":false},"excerpt":{"rendered":"<p>Maximum Sample Rate: 75 kS\/s<br \/>\n\u0428\u0438\u043d\u043d\u044b\u0439 \u0441\u043e\u0435\u0434\u0438\u043d\u0438\u0442\u0435\u043b\u044c: PXI Hybrid<br \/>\n\u041c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f \u0442\u0430\u043a\u0442\u043e\u0432\u0430\u044f \u0447\u0430\u0441\u0442\u043e\u0442\u0430: 4 \u041c\u0413\u0446<br \/>\n\u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0434\u0432\u0443\u043d\u0430\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u043d\u044b\u0445 \u0446\u0438\u0444\u0440\u043e\u0432\u044b\u0445 \u043a\u0430\u043d\u0430\u043b\u043e\u0432: 96<br \/>\n\u0426\u0438\u0444\u0440\u043e\u0432\u044b\u0435 \u0443\u0440\u043e\u0432\u043d\u0438 \u0432\u0432\u043e\u0434\u0430-\u0432\u044b\u0432\u043e\u0434\u0430: 3,3 \u0412, 5 \u0412<br \/>\n\u0414\u0438\u043d\u0430\u043c\u0438\u0447\u0435\u0441\u043a\u0430\u044f \u043e\u043f\u0435\u0440\u0430\u0442\u0438\u0432\u043d\u0430\u044f \u043f\u0430\u043c\u044f\u0442\u044c (DRAM): \u041c\u0411<br \/>\nFPGA: Virtex-5 LX30<br \/>\n\u0414\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0432\u0445\u043e\u0434\u043d\u043e\u0433\u043e \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432\u043e\u0433\u043e \u043d\u0430\u043f\u0440\u044f\u0436\u0435\u043d\u0438\u044f: \u043e\u0442 -1 \u0412 \u0434\u043e 1 \u0412<br \/>\n\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u043f\u043e\u0442\u043e\u043a\u043e\u0432\u043e\u0439 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 P2P: \u041d\u0435\u0442<br \/>\n\u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432\u044b\u0445 \u0432\u0445\u043e\u0434\u043d\u044b\u0445 \u043a\u0430\u043d\u0430\u043b\u043e\u0432: 8<br \/>\n\u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e 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