{"id":30635,"date":"2025-09-30T13:49:57","date_gmt":"2025-09-30T05:49:57","guid":{"rendered":"https:\/\/pxisource.com\/?post_type=product&#038;p=30635"},"modified":"2026-08-28T14:34:27","modified_gmt":"2026-08-28T06:34:27","slug":"pxie-7912","status":"publish","type":"product","link":"https:\/\/pxisource.com\/ru\/product\/pxie-7912\/","title":{"rendered":"PXIe-7912"},"content":{"rendered":"<p>\u0417\u0435\u043c\u043b\u044f <strong>PXIe-7912<\/strong> is a PXI FlexRIO coprocessor module designed to add programmable, real-time signal processing to PXI Express systems. It combines a Xilinx Kintex UltraScale KU040 FPGA, <strong>4 GB of onboard DRAM<\/strong> and a PCI Express Gen 3 x8 interface.<\/p>\n<p>Using peer-to-peer streaming, the PXIe-7912 can transfer data between compatible PXI Express instruments at rates up to <strong>7 \u0413\u0411\/\u0441<\/strong> without routing all data through the host controller. It is suitable for RF processing, spectral analysis, radar prototyping, data reduction, custom triggering and computationally demanding automated test systems.<\/p>\n<h3>Key Features of the PXIe-7912<\/h3>\n<ul>\n<li>FPGA Xilinx Kintex UltraScale KU040<\/li>\n<li>242,200 FPGA lookup tables<\/li>\n<li>1,920 DSP48 slices<\/li>\n<li>21.1 Mb of embedded block RAM<\/li>\n<li>4 GB onboard DRAM<\/li>\n<li>Maximum theoretical DRAM bandwidth of 17 GB\/s<\/li>\n<li>PCI Express Gen 3 x8 interface<\/li>\n<li>Peer-to-peer streaming at up to 7 GB\/s<\/li>\n<li>Eight bidirectional single-ended digital I\/O channels<\/li>\n<li>Four high-speed serial transmit channels<\/li>\n<li>Four high-speed serial receive channels<\/li>\n<li>Serial data rates from 500 Mb\/s to 16.375 Gb\/s<\/li>\n<li>60 DMA channels<\/li>\n<li>Support for PXI timing and trigger resources<\/li>\n<li>Programmable using LabVIEW FPGA<\/li>\n<li>Support for development with Xilinx Vivado<\/li>\n<\/ul>\n<h3>PXIe-7912 Technical Specifications<\/h3>\n<table>\n<tbody>\n<tr>\n<th>Product Model<\/th>\n<td>PXIe-7912<\/td>\n<\/tr>\n<tr>\n<th>Part Number<\/th>\n<td>785173-01<\/td>\n<\/tr>\n<tr>\n<th>Product Type<\/th>\n<td>\u041c\u043e\u0434\u0443\u043b\u044c \u0441\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 PXI FlexRIO<\/td>\n<\/tr>\n<tr>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<td>Xilinx Kintex UltraScale KU040<\/td>\n<\/tr>\n<tr>\n<th>FPGA Slices<\/th>\n<td>60,600<\/td>\n<\/tr>\n<tr>\n<th>Lookup Tables<\/th>\n<td>242,200<\/td>\n<\/tr>\n<tr>\n<th>DSP48 Slices<\/th>\n<td>1,920<\/td>\n<\/tr>\n<tr>\n<th>Embedded Block RAM<\/th>\n<td>21.1 Mb<\/td>\n<\/tr>\n<tr>\n<th>Onboard DRAM<\/th>\n<td>4 GB, arranged as two 2 GB banks<\/td>\n<\/tr>\n<tr>\n<th>DRAM Clock Rate<\/th>\n<td>1,064 MHz<\/td>\n<\/tr>\n<tr>\n<th>LabVIEW FPGA DRAM Clock<\/th>\n<td>267 MHz<\/td>\n<\/tr>\n<tr>\n<th>Maximum Theoretical DRAM Rate<\/th>\n<td>17 GB\/s total; 8.5 GB\/s per bank<\/td>\n<\/tr>\n<tr>\n<th>\u0428\u0438\u043d\u043d\u044b\u0439 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441<\/th>\n<td>PCI Express Gen 3 x8<\/td>\n<\/tr>\n<tr>\n<th>Maximum Peer-to-Peer Rate<\/th>\n<td>Up to 7 GB\/s<\/td>\n<\/tr>\n<tr>\n<th>DMA Channels<\/th>\n<td>60<\/td>\n<\/tr>\n<tr>\n<th>Digital I\/O Channels<\/th>\n<td>8 bidirectional single-ended channels<\/td>\n<\/tr>\n<tr>\n<th>Digital Voltage Families<\/th>\n<td>1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V<\/td>\n<\/tr>\n<tr>\n<th>Digital Output Toggle Rate<\/th>\n<td>60 MHz nominal with a 100 \u03bcA load<\/td>\n<\/tr>\n<tr>\n<th>High-Speed Serial Channels<\/th>\n<td>4 transmit and 4 receive<\/td>\n<\/tr>\n<tr>\n<th>High-Speed Serial Rate<\/th>\n<td>500 Mb\/s to 16.375 Gb\/s nominal<\/td>\n<\/tr>\n<tr>\n<th>Front Connector<\/th>\n<td>Molex Nano-Pitch I\/O<\/td>\n<\/tr>\n<tr>\n<th>Default FPGA Timebase<\/th>\n<td>80 MHz<\/td>\n<\/tr>\n<tr>\n<th>Timebase Reference<\/th>\n<td>PXI Express 100 MHz clock<\/td>\n<\/tr>\n<tr>\n<th>Maximum Power Requirement<\/th>\n<td>58 W<\/td>\n<\/tr>\n<tr>\n<th>Operating Temperature<\/th>\n<td>0\u00b0C to 55\u00b0C with adequate chassis slot cooling<\/td>\n<\/tr>\n<tr>\n<th>Dimensions<\/th>\n<td>18.8 cm \u00d7 12.9 cm, excluding connectors<\/td>\n<\/tr>\n<tr>\n<th>Weight<\/th>\n<td>190 g<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXIe-7912 Part Number and Configuration<\/h3>\n<table>\n<thead>\n<tr>\n<th>Part Number<\/th>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<th>DRAM<\/th>\n<th>PXI Interface<\/th>\n<th>Auxiliary I\/O<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>785173-01<\/td>\n<td>Kintex UltraScale KU040<\/td>\n<td>4 GB<\/td>\n<td>PCI Express Gen 3 x8<\/td>\n<td>8 GPIO and 4 TX\/4 RX high-speed serial lanes<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>The PXIe-7912 has one primary hardware configuration. Verify part number <strong>785173-01<\/strong> when requesting pricing, technical support or a replacement module.<\/p>\n<h3>Kintex UltraScale KU040 FPGA<\/h3>\n<p>The PXIe-7912 uses a Xilinx Kintex UltraScale KU040 FPGA with 242,200 lookup tables, 1,920 DSP48 slices and 21.1 Mb of embedded block RAM.<\/p>\n<p>The FPGA is suitable for a moderate amount of parallel signal processing and can implement customized algorithms directly in hardware.<\/p>\n<ul>\n<li>Digital filtering<\/li>\n<li>Fast Fourier transform processing<\/li>\n<li>Digital downconversion<\/li>\n<li>Frequency channelization<\/li>\n<li>Signal averaging<\/li>\n<li>Pulse and event detection<\/li>\n<li>Custom triggering<\/li>\n<li>Real-time data reduction<\/li>\n<li>Protocol processing<\/li>\n<li>Deterministic decision making<\/li>\n<\/ul>\n<p>Some FPGA resources are reserved for PCI Express connectivity, device configuration and board-level interfaces, so the resources available to the user are slightly lower than the total device capacity.<\/p>\n<h3>4 GB Onboard DRAM<\/h3>\n<p>The PXIe-7912 includes 4 GB of onboard DRAM arranged as two independent 2 GB banks. Each bank provides a maximum theoretical data rate of 8.5 GB\/s, producing a combined theoretical rate of 17 GB\/s.<\/p>\n<p>Onboard memory can be used for:<\/p>\n<ul>\n<li>High-speed waveform buffering<\/li>\n<li>Temporary acquisition storage<\/li>\n<li>Record-based signal processing<\/li>\n<li>Long digital delay lines<\/li>\n<li>Channel emulation<\/li>\n<li>Large lookup tables<\/li>\n<li>Multistage FPGA algorithms<\/li>\n<\/ul>\n<p>The LabVIEW FPGA memory interface simplifies access to DRAM without requiring the user to manage every low-level memory transaction.<\/p>\n<h3>7 GB\/s Peer-to-Peer Streaming<\/h3>\n<p>The PCI Express Gen 3 x8 architecture allows the PXIe-7912 to stream data to and from compatible PXI Express modules at rates up to 7 GB\/s.<\/p>\n<p>Peer-to-peer streaming transfers data directly between modules without sending it through the host controller. This reduces CPU workload and helps maintain low-latency data paths for high-throughput applications.<\/p>\n<p>The PXIe-7912 can be paired with oscilloscopes, digitizers, RF instruments, vector signal transceivers and other FPGA-enabled PXI modules.<\/p>\n<h3>FPGA Coprocessing for PXI Instruments<\/h3>\n<p>The PXIe-7912 does not contain a dedicated analog measurement front end. Instead, it acts as an FPGA coprocessor for data acquired or generated by other PXI instruments.<\/p>\n<p>A compatible source instrument can stream data to the PXIe-7912, where the FPGA processes the data before transferring results to another module, system memory or storage device.<\/p>\n<p>This architecture is useful when an existing instrument does not provide sufficient onboard FPGA resources for the required algorithm.<\/p>\n<h3>Eight Bidirectional Digital I\/O Channels<\/h3>\n<p>The front-panel Nano-Pitch connector provides eight bidirectional single-ended digital I\/O channels. Each channel supports independent direction control.<\/p>\n<p>Supported voltage families include 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The maximum nominal output toggle rate is 60 MHz with a 100 \u03bcA load.<\/p>\n<p>These lines can be used for external triggering, status signals, control interfaces and communication with custom electronics.<\/p>\n<h3>High-Speed Serial I\/O<\/h3>\n<p>The PXIe-7912 provides four high-speed serial transmit channels and four receive channels through its front-panel connector.<\/p>\n<p>The Xilinx UltraScale GTH transceivers support nominal data rates from 500 Mb\/s to 16.375 Gb\/s. They can be used for custom serial interfaces, FPGA-to-FPGA communication and high-bandwidth data transfer to external hardware.<\/p>\n<h3>PXI Timing and Trigger Resources<\/h3>\n<p>The PXIe-7912 can access multiple timing and trigger resources through the PXI Express backplane:<\/p>\n<ul>\n<li>PXI trigger lines<\/li>\n<li>PXI_CLK10<\/li>\n<li>PXI star trigger<\/li>\n<li>PXIe_DStarB<\/li>\n<li>PXIe_DStarC<\/li>\n<li>PXIe_Sync100<\/li>\n<\/ul>\n<p>These resources help coordinate FPGA processing with other acquisition, generation and RF modules in a synchronized PXI system.<\/p>\n<h3>60 DMA Channels<\/h3>\n<p>The PXIe-7912 provides 60 DMA channels for transferring data between FPGA logic and other system components. Multiple DMA channels allow FPGA applications to maintain several independent data streams.<\/p>\n<p>Appropriate DMA configuration can separate raw data, processed results, status information and control messages into independent transfer paths.<\/p>\n<h3>Typical PXIe-7912 Applications<\/h3>\n<ul>\n<li>Real-time RF signal processing<\/li>\n<li>Vector signal transceiver coprocessing<\/li>\n<li>Digital downconversion<\/li>\n<li>Wideband spectral analysis<\/li>\n<li>Radar and electronic warfare prototyping<\/li>\n<li>Channelization and signal classification<\/li>\n<li>High-speed event detection<\/li>\n<li>Data reduction before storage<\/li>\n<li>FPGA-to-FPGA streaming<\/li>\n<li>Custom protocol processing<\/li>\n<li>Hardware-in-the-loop testing<\/li>\n<li>\u0412\u0430\u043b\u0438\u0434\u0430\u0446\u0438\u044f \u043f\u043e\u043b\u0443\u043f\u0440\u043e\u0432\u043e\u0434\u043d\u0438\u043a\u043e\u0432<\/li>\n<li>High-throughput automated test systems<\/li>\n<\/ul>\n<h3>\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u043d\u043e\u0433\u043e \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0435\u043d\u0438\u044f<\/h3>\n<p>The PXIe-7912 is supported by NI LabVIEW Instrument Design Libraries for FlexRIO. These libraries provide interfaces, documentation and sample projects for configuring the device and developing real-time FPGA applications.<\/p>\n<ul>\n<li>\u041b\u0430\u0431\u0412\u044c\u044e<\/li>\n<li>LabVIEW FPGA Module<\/li>\n<li>Instrument Design Libraries for FlexRIO<\/li>\n<li>NI FlexRIO driver<\/li>\n<li>Xilinx Vivado development tools<\/li>\n<\/ul>\n<p>Engineers can develop FPGA logic through LabVIEW FPGA or use supported Xilinx development workflows when integrating existing HDL code and specialized FPGA intellectual property.<\/p>\n<h3>PXI Express Chassis Requirements<\/h3>\n<p>The PXIe-7912 requires a compatible PXI Express chassis and a Gen 3 x8-capable peripheral slot to achieve maximum data-transfer performance.<\/p>\n<p>The chassis slot must provide at least 58 W of cooling capacity. Not every chassis supporting 58 W slot cooling can maintain the full 0\u00b0C to 55\u00b0C module operating range, so verify the chassis specifications.<\/p>\n<p>Browse compatible <a href=\"https:\/\/pxisource.com\/ru\/product-category\/%d0%bd%d0%b8\/pxi-%d1%81%d0%b8%d1%81%d1%82%d0%b5%d0%bc%d1%81\/%d0%bc%d0%be%d0%b4%d1%83%d0%bb%d0%b8-pxi\/\">NI PXI modules and system components<\/a> when configuring a complete FPGA processing platform.<\/p>\n<h3>PXIe-7912 Troubleshooting<\/h3>\n<h4>Why is the peer-to-peer transfer rate lower than 7 GB\/s?<\/h4>\n<p>Confirm that both modules support peer-to-peer streaming and are installed in chassis slots with a compatible Gen 3 x8 data path. Chassis topology, FPGA logic and transfer-block size can affect throughput.<\/p>\n<h4>Why is the high-speed serial interface unavailable?<\/h4>\n<p>Verify that the FPGA personality enables the required GTH transceivers and that the cable, connector and external device support the configured line rate.<\/p>\n<h4>Why is the FPGA compilation unsuccessful?<\/h4>\n<p>Confirm that the design fits within the KU040 lookup tables, DSP slices and block RAM. Reduce parallel processing or memory requirements if the design exceeds the available resources.<\/p>\n<h4>Why does the module revert to its default FPGA personality?<\/h4>\n<p>A large FPGA design operating at high clock rates can exceed the module\u2019s available power. Verify the chassis cooling capacity and optimize the FPGA implementation.<\/p>\n<h4>Why is the module not visible in software?<\/h4>\n<p>Confirm that it is installed in a compatible PXI Express slot. Check the chassis, controller, FlexRIO driver, operating system and software version compatibility.<\/p>\n<h4>Why is DRAM performance lower than expected?<\/h4>\n<p>DRAM performance depends on access patterns, transfer size, arbitration and FPGA logic. Sequential, burst-based transfers generally provide better throughput than frequent small or random transactions.<\/p>\n<h4>Can the PXIe-7912 acquire analog signals directly?<\/h4>\n<p>No. The PXIe-7912 is a coprocessor module without an integrated analog front end. It processes data received from other PXI instruments or external digital interfaces.<\/p>\n<h3>PXIe-7912 Comparison<\/h3>\n<table>\n<thead>\n<tr>\n<th>\u041c\u043e\u0434\u0435\u043b\u044c<\/th>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<th>DRAM<\/th>\n<th>PXI Interface<\/th>\n<th>Auxiliary I\/O<\/th>\n<th>Primary Difference<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>PXIe-7912<\/td>\n<td>Kintex UltraScale KU040<\/td>\n<td>4 GB<\/td>\n<td>Gen 3 x8<\/td>\n<td>8 GPIO and 4 TX\/4 RX HSS<\/td>\n<td>Moderate FPGA processing capacity with DRAM and serial I\/O<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7911\/\">PXIe-7911<\/a><\/td>\n<td>Kintex UltraScale KU035<\/td>\n<td>\u041d\u0438\u0447\u0435\u0433\u043e<\/td>\n<td>Gen 3 x8<\/td>\n<td>No front-panel auxiliary I\/O<\/td>\n<td>Smaller FPGA configuration without external DRAM<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7915\/\">PXIe-7915<\/a><\/td>\n<td>Kintex UltraScale KU060<\/td>\n<td>4 GB<\/td>\n<td>Gen 3 x8<\/td>\n<td>8 GPIO and 4 TX\/4 RX HSS<\/td>\n<td>Larger FPGA for more demanding parallel processing<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7976\/\">PXIe-7976<\/a><\/td>\n<td>Kintex-7 410T<\/td>\n<td>2 GB<\/td>\n<td>Gen 2 x8<\/td>\n<td>FlexRIO adapter interface<\/td>\n<td>Designed for use with modular FlexRIO adapter modules<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7902\/\">PXIe-7902<\/a><\/td>\n<td>Virtex-7 485T<\/td>\n<td>2 GB<\/td>\n<td>Gen 2 x8<\/td>\n<td>24 TX\/RX serial lanes<\/td>\n<td>Dedicated high-speed serial protocol testing<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>Recommended Related Products<\/h3>\n<ul>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7911\/\"><strong>PXIe-7911<\/strong><\/a> \u2013 Suitable for applications requiring a smaller KU035 FPGA without onboard DRAM or auxiliary I\/O.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7915\/\"><strong>PXIe-7915<\/strong><\/a> \u2013 Recommended when the larger KU060 FPGA is required for more complex RF and signal-processing algorithms.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7976\/\"><strong>PXIe-7976<\/strong><\/a> \u2013 Provides a modular FlexRIO FPGA platform for use with compatible analog and digital adapter modules.<\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7902\/\"><strong>PXIe-7902<\/strong><\/a> \u2013 Designed for applications requiring 24 high-speed serial transmit and receive lanes.<\/li>\n<\/ul>\n<h3>How to Select the Right PXI FPGA Coprocessor<\/h3>\n<ul>\n<li>Choose the PXIe-7912 for moderate FPGA processing with 4 GB DRAM and front-panel GPIO and serial I\/O.<\/li>\n<li>Choose the PXIe-7911 when onboard DRAM and auxiliary I\/O are unnecessary.<\/li>\n<li>Choose the PXIe-7915 for larger algorithms requiring additional LUTs, DSP slices and block RAM.<\/li>\n<li>Choose a PXIe-797x module when the application requires a modular FlexRIO analog or digital adapter.<\/li>\n<li>Choose a high-speed serial instrument when multiple dedicated serial protocol lanes are required.<\/li>\n<\/ul>\n<h3>Why Choose the PXIe-7912?<\/h3>\n<p>The PXIe-7912 combines a programmable KU040 FPGA, 4 GB DRAM, Gen 3 x8 PXI connectivity and high-speed serial I\/O in a compact coprocessor module. It adds deterministic processing capacity without requiring replacement of the source measurement instrument.<\/p>\n<p>Its peer-to-peer architecture is particularly valuable in systems where large data streams must be processed in real time before transfer to the host controller or storage device.<\/p>\n<h3>Frequently Asked Questions<\/h3>\n<h4>What is the PXIe-7912?<\/h4>\n<p>The PXIe-7912 is a Kintex UltraScale KU040 FPGA coprocessor module that adds real-time signal processing and high-speed data movement to PXI Express systems.<\/p>\n<h4>What is the PXIe-7912 part number?<\/h4>\n<p>The standard NI part number is <strong>785173-01<\/strong>.<\/p>\n<h4>How much onboard memory does it provide?<\/h4>\n<p>The PXIe-7912 includes 4 GB of DRAM arranged as two 2 GB banks.<\/p>\n<h4>What is the maximum peer-to-peer streaming rate?<\/h4>\n<p>The module can stream data to and from compatible PXI Express devices at rates up to 7 GB\/s.<\/p>\n<h4>Does the PXIe-7912 have analog inputs?<\/h4>\n<p>No. It is an FPGA coprocessor rather than a measurement instrument. Analog data must be supplied by another compatible PXI module.<\/p>\n<h4>What FPGA does the PXIe-7912 use?<\/h4>\n<p>It uses a Xilinx Kintex UltraScale KU040 FPGA with 242,200 LUTs, 1,920 DSP48 slices and 21.1 Mb of block RAM.<\/p>\n<h4>Does it provide digital I\/O?<\/h4>\n<p>Yes. It provides eight bidirectional GPIO channels plus four high-speed serial transmit and four receive channels.<\/p>\n<h4>Can the PXIe-7912 be programmed with Vivado?<\/h4>\n<p>Yes. Depending on the development workflow, it can be programmed using LabVIEW FPGA or supported Xilinx Vivado tools.<\/p>\n<h4>What is the difference between the PXIe-7912 and PXIe-7915?<\/h4>\n<p>Both provide 4 GB DRAM, Gen 3 x8 connectivity and similar auxiliary I\/O. The PXIe-7915 uses a larger KU060 FPGA for more demanding processing.<\/p>\n<h4>Can the PXIe-7912 operate independently?<\/h4>\n<p>No. It requires a compatible PXI Express chassis, controller or peer-to-peer source module and the appropriate software environment.<\/p>\n<h3>Request a Quote for the PXIe-7912<\/h3>\n<p>Contact us for current availability, lead time and project pricing for the <strong>PXIe-7912 PXI FlexRIO Coprocessor Module<\/strong>. We can also help verify compatible PXI chassis, controllers, RF instruments and peer-to-peer streaming configurations.<\/p>","protected":false},"excerpt":{"rendered":"<p>\u0411\u043b\u043e\u043a \u041e\u0417\u0423 (BRAM): 21 \u041c\u0431\u0438\u0442<br \/>\nDSP-\u0441\u0440\u0435\u0437\u044b: 1920<br \/>\nFPGA-\u0441\u043b\u0430\u0439\u0441\u044b: 60600<br \/>\n\u0414\u0438\u043d\u0430\u043c\u0438\u0447\u0435\u0441\u043a\u0430\u044f \u041e\u0417\u0423 (DRAM): 4 \u0413\u0411<br \/>\nFPGA: Kintex UltraScale KU040<br \/>\nPXI-\u0441\u043e\u0435\u0434\u0438\u043d\u0435\u043d\u0438\u0435: PCI-Express Gen3 x 8<br \/>\n\u0412\u0441\u043f\u043e\u043c\u043e\u0433\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u0432\u0432\u043e\u0434-\u0432\u044b\u0432\u043e\u0434: 4 HSS, 8 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