{"id":30585,"date":"2025-09-30T11:30:32","date_gmt":"2025-09-30T03:30:32","guid":{"rendered":"https:\/\/pxisource.com\/?post_type=product&#038;p=30585"},"modified":"2026-08-31T12:28:35","modified_gmt":"2026-08-31T04:28:35","slug":"pxie-7962","status":"publish","type":"product","link":"https:\/\/pxisource.com\/ru\/product\/pxie-7962\/","title":{"rendered":"PXIe-7962"},"content":{"rendered":"<h3>PXIe-7962R Virtex-5 SX50T FlexRIO FPGA Module<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <strong>PXIe-7962R<\/strong>, also listed as the <strong>PXIe-7962<\/strong>, is a PXI Express FlexRIO FPGA module for custom high-speed data acquisition, real-time signal processing, protocol implementation and hardware-in-the-loop testing. It combines a user-programmable Xilinx Virtex-5 SX50T FPGA with 512 MB of onboard DRAM and a high-speed interface for compatible FlexRIO adapter modules.<\/p>\n<p>The PXIe-7962R does not provide fixed analog or digital measurement channels by itself. An installed FlexRIO adapter module determines the external I\/O type, channel count, sample rate, resolution, voltage range and connector configuration. This architecture allows engineers to create application-specific instruments using a common FPGA carrier.<\/p>\n<h3>Key Features of the PXIe-7962R<\/h3>\n<ul>\n<li>Xilinx Virtex-5 SX50T user-programmable FPGA<\/li>\n<li>8,160 FPGA slices<\/li>\n<li>32,640 lookup tables and flip-flops<\/li>\n<li>288 DSP48 arithmetic slices<\/li>\n<li>4,752 kbits of embedded block RAM<\/li>\n<li>512 MB onboard DRAM<\/li>\n<li>Two independent 256 MB DRAM banks<\/li>\n<li>Up to 1.6 GB\/s bandwidth per DRAM bank<\/li>\n<li>132 single-ended I\/O lines or 66 differential LVDS pairs<\/li>\n<li>PCI Express Gen 1 \u00d74 backplane link<\/li>\n<li>More than 800 MB\/s module streaming capability<\/li>\n<li>More than 1.4 GB\/s aggregate bidirectional streaming<\/li>\n<li>Up to 16 DMA data streams<\/li>\n<li>Peer-to-peer data streaming support<\/li>\n<li>PXIe_CLK100 reference-clock support<\/li>\n<li>LabVIEW FPGA programming support<\/li>\n<\/ul>\n<h3>PXIe-7962R Technical Specifications<\/h3>\n<table>\n<tbody>\n<tr>\n<th>Product Model<\/th>\n<td>PXIe-7962R \/ PXIe-7962<\/td>\n<\/tr>\n<tr>\n<th>Part Number<\/th>\n<td>781206-01<\/td>\n<\/tr>\n<tr>\n<th>Product Type<\/th>\n<td>PXI Express FlexRIO FPGA module<\/td>\n<\/tr>\n<tr>\n<th>\u0424\u041f\u0413\u0410<\/th>\n<td>Xilinx Virtex-5 SX50T<\/td>\n<\/tr>\n<tr>\n<th>FPGA Slices<\/th>\n<td>8,160<\/td>\n<\/tr>\n<tr>\n<th>Lookup Tables and Flip-Flops<\/th>\n<td>32,640<\/td>\n<\/tr>\n<tr>\n<th>DSP48 Slices<\/th>\n<td>288<\/td>\n<\/tr>\n<tr>\n<th>DSP Multiplier Size<\/th>\n<td>25 \u00d7 18 bits<\/td>\n<\/tr>\n<tr>\n<th>Embedded Block RAM<\/th>\n<td>4,752 kbits<\/td>\n<\/tr>\n<tr>\n<th>Onboard DRAM<\/th>\n<td>512 MB total<\/td>\n<\/tr>\n<tr>\n<th>DRAM Configuration<\/th>\n<td>Two banks, 256 MB per bank<\/td>\n<\/tr>\n<tr>\n<th>DRAM Bandwidth<\/th>\n<td>Up to 1.6 GB\/s per bank<\/td>\n<\/tr>\n<tr>\n<th>Adapter-Module Interface<\/th>\n<td>132 single-ended lines or 66 differential LVDS pairs<\/td>\n<\/tr>\n<tr>\n<th>PXI Backplane Interface<\/th>\n<td>PCI Express Gen 1 \u00d74<\/td>\n<\/tr>\n<tr>\n<th>Default FPGA Timebase<\/th>\n<td>40 MHz<\/td>\n<\/tr>\n<tr>\n<th>Reference Clock<\/th>\n<td>PXI Express 100 MHz reference clock, PXIe_CLK100<\/td>\n<\/tr>\n<tr>\n<th>Timebase Accuracy<\/th>\n<td>\u00b150 ppm<\/td>\n<\/tr>\n<tr>\n<th>Streaming Rate<\/th>\n<td>More than 800 MB\/s into or out of the module<\/td>\n<\/tr>\n<tr>\n<th>Simultaneous Bidirectional Streaming<\/th>\n<td>More than 700 MB\/s per direction<\/td>\n<\/tr>\n<tr>\n<th>Aggregate Bidirectional Rate<\/th>\n<td>More than 1.4 GB\/s<\/td>\n<\/tr>\n<tr>\n<th>Maximum DMA Streams<\/th>\n<td>Up to 16<\/td>\n<\/tr>\n<tr>\n<th>Peer-to-Peer Streaming<\/th>\n<td>Supported<\/td>\n<\/tr>\n<tr>\n<th>Programming Environment<\/th>\n<td>LabVIEW FPGA Module<\/td>\n<\/tr>\n<tr>\n<th>Device Driver<\/th>\n<td>NI FlexRIO<\/td>\n<\/tr>\n<tr>\n<th>Operating Temperature<\/th>\n<td>0\u00b0C to 55\u00b0C<\/td>\n<\/tr>\n<tr>\n<th>Dimensions<\/th>\n<td>Approximately 16.1 cm \u00d7 10.8 cm<\/td>\n<\/tr>\n<tr>\n<th>Weight<\/th>\n<td>Approximately 213 g<\/td>\n<\/tr>\n<tr>\n<th>Module Format<\/th>\n<td>3U PXI Express module<\/td>\n<\/tr>\n<tr>\n<th>Product Status<\/th>\n<td>Discontinued<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXIe-7962R Part Number and Identification<\/h3>\n<table>\n<tbody>\n<tr>\n<th>Identifier Type<\/th>\n<th>Number<\/th>\n<th>\u041e\u043f\u0438\u0441\u0430\u043d\u0438\u0435<\/th>\n<\/tr>\n<tr>\n<td>Orderable Part Number<\/td>\n<td>781206-01<\/td>\n<td>PXIe-7962R FlexRIO FPGA module with Virtex-5 SX50T and 512 MB RAM<\/td>\n<\/tr>\n<tr>\n<td>Assembly Number<\/td>\n<td>198733-01L<\/td>\n<td>PXIe-7962R circuit-card assembly with 66 LVDS pairs and SX50T FPGA<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Use <strong>781206-01<\/strong> when requesting a quotation for the complete module. The 198733-01L number identifies the circuit-card assembly and is not normally used as the commercial ordering number.<\/p>\n<h3>FlexRIO Modular Architecture<\/h3>\n<p>The FlexRIO architecture separates FPGA processing from application-specific I\/O. The PXIe-7962R supplies the FPGA, onboard memory, timing resources and PXI Express communication, while a compatible adapter module provides the required external signal interface.<\/p>\n<p>This modular approach allows the PXIe-7962R to support applications involving analog input, analog output, high-speed digital I\/O, RF conversion and camera connectivity. The available functionality depends entirely on the selected adapter.<\/p>\n<h3>Virtex-5 SX50T FPGA<\/h3>\n<p>The PXIe-7962R uses a Xilinx Virtex-5 SX50T FPGA optimized for digital signal processing. FPGA algorithms execute directly in hardware, providing deterministic timing and parallel operation without relying on operating-system scheduling.<\/p>\n<p>The SX50T target provides enough resources for many legacy acquisition, generation, filtering, protocol and control applications while consuming fewer resources than the larger SX95T devices used in the PXIe-7965R and PXIe-7966R.<\/p>\n<h3>8,160 FPGA Slices<\/h3>\n<p>The FPGA contains 8,160 slices that can implement state machines, timing engines, data routing, custom protocols and real-time control logic. NI documentation also describes the device as providing 32,640 lookup tables and flip-flops.<\/p>\n<p>Usable capacity depends on the FPGA program, clock rates, data types, memory configuration and compilation optimization. Review the compilation report to determine actual resource utilization.<\/p>\n<h3>288 DSP48 Slices<\/h3>\n<p>The PXIe-7962R provides 288 DSP48 slices for hardware-accelerated multiplication and signal-processing operations. These resources support finite impulse response filters, mixers, digital downconversion and other mathematical algorithms.<\/p>\n<p>DSP slices can operate in parallel, allowing the FPGA to process multiple samples or channels simultaneously when the design and clock rate permit.<\/p>\n<h3>Embedded Block RAM<\/h3>\n<p>The Virtex-5 SX50T includes 4,752 kbits of embedded block RAM. This low-latency FPGA memory can implement FIFOs, lookup tables, delay lines, buffers and temporary algorithm storage.<\/p>\n<p>Block RAM offers deterministic access but has limited capacity. Larger waveform buffers and data sets should normally be stored in the module\u2019s external DRAM.<\/p>\n<h3>512 MB Onboard DRAM<\/h3>\n<p>The PXIe-7962R includes 512 MB of onboard DRAM divided into two independent 256 MB banks. Each bank can provide bandwidth up to approximately 1.6 GB\/s under supported access conditions.<\/p>\n<p>The DRAM can store acquired waveforms, generation data or intermediate processing results. Using separate banks can help distribute memory traffic and support simultaneous acquisition and processing operations.<\/p>\n<h3>Efficient DRAM Programming<\/h3>\n<p>External DRAM has greater capacity than FPGA block RAM but also has higher access latency. FPGA applications should use suitable request, retrieval and buffering logic to maintain throughput.<\/p>\n<p>Invalid address ranges and poorly structured access patterns can cause errors or reduce performance. Enable and monitor error terminals when developing custom DRAM interfaces.<\/p>\n<h3>132 Single-Ended or 66 Differential Lines<\/h3>\n<p>The interface between the PXIe-7962R and its adapter module provides 132 single-ended I\/O lines that can also be configured as 66 differential LVDS pairs.<\/p>\n<p>These lines are part of the internal FlexRIO adapter interface. They are not directly accessible as front-panel digital I\/O unless the installed adapter module provides the required external connections and electrical conditioning.<\/p>\n<h3>Compatible FlexRIO Adapter Modules<\/h3>\n<p>The PXIe-7962R can be paired with compatible first-generation FlexRIO adapter modules. Examples include digitizers, signal generators, high-speed digital modules and camera-interface adapters.<\/p>\n<p>One documented system configuration combines the PXIe-7962R with the NI-6585 200 MHz, 32-channel LVDS digital adapter. Compatibility must still be verified for the specific adapter, driver version and LabVIEW FPGA project.<\/p>\n<h3>Adapter Module Determines Measurement Specifications<\/h3>\n<p>The PXIe-7962R does not independently define analog sample rate, resolution, voltage range or digital logic levels. Those specifications are determined by the attached adapter module.<\/p>\n<p>When ordering a complete FlexRIO system, identify both the FPGA carrier and adapter. The PXIe-7962R alone cannot directly acquire or generate an external signal.<\/p>\n<h3>PCI Express Gen 1 \u00d74 Interface<\/h3>\n<p>The PXIe-7962R communicates with the PXI Express backplane through a PCI Express Gen 1 \u00d74 link. This connection supports high-speed transfer between the FPGA module and the PXI controller.<\/p>\n<p>Actual host-transfer performance depends on the chassis topology, controller, slot bandwidth, DMA configuration and efficiency of the FPGA and host applications.<\/p>\n<h3>\u0412\u044b\u0441\u043e\u043a\u043e\u0441\u043a\u043e\u0440\u043e\u0441\u0442\u043d\u0430\u044f \u043f\u043e\u0442\u043e\u043a\u043e\u0432\u0430\u044f \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445<\/h3>\n<p>The PXIe-7962R can stream data at more than 800 MB\/s into or out of the module in a supported PXI Express system. The FPGA determines how data is formatted, buffered and distributed across the available DMA channels.<\/p>\n<p>When streaming in both directions simultaneously, the module can exceed 700 MB\/s per direction and achieve an aggregate rate above 1.4 GB\/s.<\/p>\n<h3>Up to 16 DMA Streams<\/h3>\n<p>The PXIe-7962R supports as many as 16 DMA channels. Separate channels can carry raw acquisition data, processed results, generation waveforms and control information.<\/p>\n<p>The total throughput remains limited by the module and system data path. Adding more DMA streams divides the available bandwidth rather than increasing the physical link capacity.<\/p>\n<h3>Peer-to-Peer Streaming<\/h3>\n<p>NI peer-to-peer technology allows the PXIe-7962R to exchange data directly with compatible PXI Express instruments without routing every transfer through the controller CPU and host memory.<\/p>\n<p>A compatible digitizer can stream acquired samples directly to the FPGA for processing. The FPGA can then transfer the processed information to another supported instrument or return a reduced data set to the controller.<\/p>\n<h3>Benefits of FPGA Peer-to-Peer Processing<\/h3>\n<p>Direct instrument-to-instrument transfer can reduce host workload and system latency. It is useful for real-time signal processing, closed-loop testing, high-speed triggering and applications that generate more raw data than the controller should process continuously.<\/p>\n<p>Peer-to-peer operation depends on the chassis topology, compatible writer and reader endpoints, driver versions and FPGA configuration.<\/p>\n<h3>PXI Express \u0422\u0430\u0439\u043c\u0438\u043d\u0433 \u0438 \u0421\u0438\u043d\u0445\u0440\u043e\u043d\u0438\u0437\u0430\u0446\u0438\u044f<\/h3>\n<p>The module uses the PXIe_CLK100 reference clock and provides a default FPGA timebase of 40 MHz. FPGA-derived clocks can be created for application-specific processing and I\/O timing.<\/p>\n<p>PXI trigger resources allow the FPGA program to coordinate events with digitizers, waveform generators and other instruments installed in the same chassis.<\/p>\n<h3>Deterministic Hardware Processing<\/h3>\n<p>FPGA algorithms execute with clock-cycle timing and do not depend on software thread scheduling. This makes the PXIe-7962R useful for precise triggering, custom protocols and low-latency decision-making.<\/p>\n<p>Multiple processing functions can operate concurrently, including acquisition, filtering, event detection, memory access and DMA transfer.<\/p>\n<h3>LabVIEW FPGA Programming<\/h3>\n<p>The PXIe-7962R is programmed using the LabVIEW FPGA Module and compatible NI FlexRIO software. Developers create FPGA logic, compile it for the Virtex-5 SX50T target and download the resulting bitfile to the module.<\/p>\n<p>Recompiling older projects may require a compatible legacy LabVIEW FPGA release and Xilinx compilation tools. Verify the complete software stack before upgrading an established system.<\/p>\n<h3>Existing FPGA Bitfiles<\/h3>\n<p>A previously compiled bitfile may continue to run without recompilation when the module, adapter, NI FlexRIO driver and host application remain compatible.<\/p>\n<p>Bitfiles are compiled for a specific FPGA target and adapter configuration. A file created for the PXIe-7965R, PXIe-7966R or newer Kintex-7 module should not be loaded onto the PXIe-7962R unless the project is migrated and recompiled.<\/p>\n<h3>Typical PXIe-7962R Applications<\/h3>\n<ul>\n<li>\u0412\u044b\u0441\u043e\u043a\u043e\u0441\u043a\u043e\u0440\u043e\u0441\u0442\u043d\u043e\u0439 \u0441\u0431\u043e\u0440 \u0434\u0430\u043d\u043d\u044b\u0445<\/li>\n<li>Inline digital signal processing<\/li>\n<li>Custom digital protocol implementation<\/li>\n<li>High-speed digital I\/O<\/li>\n<li>Software-defined radio processing<\/li>\n<li>Radar and communications testing<\/li>\n<li>Machine vision and camera interfacing<\/li>\n<li>Hardware-in-the-loop testing<\/li>\n<li>Real-time triggering and event detection<\/li>\n<li>Peer-to-peer instrument streaming<\/li>\n<li>Research instrumentation<\/li>\n<li>Laboratory automation<\/li>\n<\/ul>\n<h3>High-Speed Data Acquisition<\/h3>\n<p>When combined with a compatible digitizer adapter, the PXIe-7962R can acquire and process data directly in the FPGA. Algorithms can filter, decimate, trigger or reduce the information before it is sent to the controller.<\/p>\n<p>This FPGA preprocessing reduces host bandwidth when the application only needs detected events, calculated parameters or selected waveform segments.<\/p>\n<h3>Real-Time Signal Processing<\/h3>\n<p>The 288 DSP48 slices can implement parallel filtering, mixing and mathematical processing. Incoming samples can be processed continuously with deterministic timing.<\/p>\n<p>Typical algorithms include finite impulse response filtering, digital downconversion, pulse detection and custom modulation processing.<\/p>\n<h3>Custom Digital Interfaces<\/h3>\n<p>With an appropriate digital adapter, the PXIe-7962R can implement proprietary and nonstandard communication protocols. FPGA logic provides direct control over timing, framing and signal-response behavior.<\/p>\n<p>This capability is valuable when testing devices that cannot be addressed by a conventional digital pattern instrument.<\/p>\n<h3>Machine Vision Applications<\/h3>\n<p>A compatible camera adapter allows the module to receive and process image data in hardware. FPGA logic can perform thresholding, region extraction and other pixel-level operations before image data reaches the controller.<\/p>\n<p>Verify the camera standard, adapter compatibility and required pixel-data rate when configuring the system.<\/p>\n<h3>Hardware-in-the-Loop Testing<\/h3>\n<p>The PXIe-7962R can execute deterministic control logic and custom signal-processing functions within a hardware-in-the-loop platform. Peer-to-peer transfer can connect the FPGA with supported digitizers and signal generators.<\/p>\n<p>System latency depends on the adapter, FPGA program, memory access and communication architecture.<\/p>\n<h3>PXIe-7962R Troubleshooting<\/h3>\n<h4>The PXIe-7962R Is Not Detected in NI MAX<\/h4>\n<p>Confirm that the module is fully installed in a compatible PXI Express slot. Check chassis power, controller communication and the installed NI FlexRIO software, then rescan the system in NI Measurement &amp; Automation Explorer.<\/p>\n<h4>The Adapter Module Is Not Recognized<\/h4>\n<p>Verify that the adapter is compatible and correctly attached to the PXIe-7962R. Check the adapter documentation and required FlexRIO driver version.<\/p>\n<h4>The FPGA Bitfile Will Not Download<\/h4>\n<p>Confirm that the bitfile was compiled for the PXIe-7962R and the installed adapter. A bitfile built for a different FPGA carrier cannot normally be used.<\/p>\n<h4>The FPGA Project Does Not Compile<\/h4>\n<p>Check the LabVIEW, LabVIEW FPGA, NI FlexRIO and Xilinx tool versions. Virtex-5 targets may require a legacy compilation environment.<\/p>\n<h4>DMA Throughput Is Lower Than Expected<\/h4>\n<p>Review DMA buffer sizes, controller performance, chassis topology, host memory allocation and FPGA loop timing. Confirm that the selected slot provides a suitable PXI Express data path.<\/p>\n<h4>Onboard DRAM Access Produces Errors<\/h4>\n<p>Check the memory address range, request sequence, retrieval logic and buffering. Monitor error terminals to identify invalid or out-of-range accesses.<\/p>\n<h4>Peer-to-Peer Streaming Does Not Start<\/h4>\n<p>Confirm that both instruments support NI peer-to-peer streaming and that the chassis provides a valid route. Check endpoint configuration, FIFO data type and writer-to-reader compatibility.<\/p>\n<h4>The FPGA Design Exceeds Available Resources<\/h4>\n<p>Review lookup-table, flip-flop, DSP and block-RAM use in the compilation report. Reduce parallel logic, reuse arithmetic resources or move large buffers to onboard DRAM.<\/p>\n<h4>Timing Requirements Are Not Met<\/h4>\n<p>Review the critical paths in the FPGA compilation report. Reduce combinational complexity, add pipelining or use additional clock cycles where permitted.<\/p>\n<h4>The Module Becomes Unstable During Continuous Processing<\/h4>\n<p>Check chassis airflow and fan configuration. Sustained FPGA processing, DRAM traffic and high-speed adapter operation can increase thermal load.<\/p>\n<h3>PXIe-7962R Comparison with Similar FlexRIO FPGA Modules<\/h3>\n<table>\n<tbody>\n<tr>\n<th>\u041c\u043e\u0434\u0435\u043b\u044c<\/th>\n<th>FPGA and Memory<\/th>\n<th>Best Suited For<\/th>\n<\/tr>\n<tr>\n<td>PXIe-7961R<\/td>\n<td>Virtex-5 SX50T, no onboard DRAM<\/td>\n<td>SX50T applications that do not require large waveform buffers<\/td>\n<\/tr>\n<tr>\n<td>PXIe-7962R<\/td>\n<td>Virtex-5 SX50T, 512 MB DRAM<\/td>\n<td>Legacy signal-processing applications requiring external FPGA memory<\/td>\n<\/tr>\n<tr>\n<td>PXIe-7965R<\/td>\n<td>Virtex-5 SX95T, 512 MB DRAM<\/td>\n<td>Applications requiring more FPGA and DSP resources<\/td>\n<\/tr>\n<tr>\n<td>PXIe-7966R<\/td>\n<td>Virtex-5 SX95T-2, 512 MB DRAM<\/td>\n<td>Highest-performance target in the PXIe-796x family<\/td>\n<\/tr>\n<tr>\n<td>PXIe-7976R<\/td>\n<td>Kintex-7 K410T, 2 GB DRAM<\/td>\n<td>Newer applications requiring substantially more processing and memory<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h3>PXIe-7962R vs PXIe-7961R<\/h3>\n<p>The PXIe-7962R and <a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7961\/\">PXIe-7961R<\/a> use the same Virtex-5 SX50T FPGA. The primary difference is that the PXIe-7962R includes 512 MB of onboard DRAM, while the PXIe-7961R does not provide external DRAM.<\/p>\n<p>Choose the PXIe-7962R when the application requires large acquisition buffers, waveform storage or intermediate processing memory.<\/p>\n<h3>PXIe-7962R vs PXIe-7965R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7965\/\">PXIe-7965R<\/a> uses a larger Virtex-5 SX95T FPGA with 14,720 slices, 640 DSP48 slices and 8,784 kbits of block RAM. Both modules include 512 MB of DRAM.<\/p>\n<p>Select the PXIe-7965R for larger algorithms and more parallel DSP processing. Choose the PXIe-7962R when its SX50T resources are sufficient for the validated legacy application.<\/p>\n<h3>PXIe-7962R vs PXIe-7966R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7966\/\">PXIe-7966R<\/a> uses the larger SX95T FPGA with a faster -2 speed grade. It provides more than twice the DSP48 resources of the PXIe-7962R.<\/p>\n<p>The PXIe-7966R is preferable for complex high-throughput signal processing. The PXIe-7962R provides a lower-resource SX50T target with the same total DRAM capacity.<\/p>\n<h3>PXIe-7962R vs PXIe-7976R<\/h3>\n<p>\u0417\u0435\u043c\u043b\u044f <a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7976\/\">PXIe-7976R<\/a> uses a newer Kintex-7 K410T FPGA, includes 2 GB of DRAM and provides substantially greater FPGA and data-transfer performance.<\/p>\n<p>NI identified the PXIe-7976R as a replacement path for discontinued PXIe-7962R systems. Migration generally requires FPGA-code modification, recompilation and compatibility testing.<\/p>\n<h3>Recommended Related Products<\/h3>\n<ul>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7961\/\">PXIe-7961R Virtex-5 SX50T FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7965\/\">PXIe-7965R Virtex-5 SX95T FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7966\/\">PXIe-7966R Virtex-5 SX95T-2 FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7972\/\">PXIe-7972R Kintex-7 FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/pxie-7976\/\">PXIe-7976R Kintex-7 K410T FlexRIO FPGA Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product\/ni-6585\/\">NI-6585 200 MHz LVDS FlexRIO Adapter Module<\/a><\/li>\n<li><a href=\"https:\/\/pxisource.com\/ru\/product-category\/%d0%bd%d0%b8\/pxi-%d1%81%d0%b8%d1%81%d1%82%d0%b5%d0%bc%d1%81\/%d0%bc%d0%be%d0%b4%d1%83%d0%bb%d0%b8-pxi\/\">View More NI PXI and PXI Express Modules<\/a><\/li>\n<\/ul>\n<h3>Selecting the Right FlexRIO FPGA Module<\/h3>\n<p>Choose the PXIe-7962R when maintaining an existing system developed for the Virtex-5 SX50T target and the application requires 512 MB of onboard DRAM.<\/p>\n<p>Select the PXIe-7965R or PXIe-7966R when more Virtex-5 processing resources are required. For new designs, consider the PXIe-7976R or a current FlexRIO integrated-I\/O module, subject to adapter and software compatibility.<\/p>\n<h3>Purchasing a Discontinued PXIe-7962R<\/h3>\n<p>The PXIe-7962R is discontinued and no longer manufactured by NI. Available inventory may consist of unused surplus, previously installed or refurbished modules.<\/p>\n<p>Before ordering, verify the 781206-01 part number, serial number, adapter compatibility and software requirements. A used module should be tested for PXI detection, FPGA bitfile download, both DRAM banks, DMA transfer, peer-to-peer communication and adapter operation.<\/p>\n<h3>Why Choose the PXIe-7962R?<\/h3>\n<ul>\n<li>Maintains compatibility with legacy SX50T FlexRIO applications<\/li>\n<li>Provides 288 DSP48 slices for real-time processing<\/li>\n<li>Includes 512 MB of onboard DRAM<\/li>\n<li>Supports modular analog, digital and camera I\/O adapters<\/li>\n<li>Streams more than 800 MB\/s in supported systems<\/li>\n<li>Supports up to 16 DMA channels<\/li>\n<li>Provides peer-to-peer instrument communication<\/li>\n<li>Supports deterministic FPGA timing and control<\/li>\n<li>Integrates with LabVIEW FPGA and PXI Express systems<\/li>\n<\/ul>\n<h3>Frequently Asked Questions<\/h3>\n<h4>What Is the PXIe-7962R?<\/h4>\n<p>The PXIe-7962R is a PXI Express FlexRIO FPGA carrier module with a Virtex-5 SX50T FPGA and 512 MB of onboard DRAM.<\/p>\n<h4>Are PXIe-7962 and PXIe-7962R the Same Product?<\/h4>\n<p>Yes. Some listings omit the R, but both names refer to the same reconfigurable FlexRIO FPGA module.<\/p>\n<h4>What Is the PXIe-7962R Part Number?<\/h4>\n<p>The standard commercial part number is <strong>781206-01<\/strong>.<\/p>\n<h4>Which FPGA Does the PXIe-7962R Use?<\/h4>\n<p>The module uses a Xilinx Virtex-5 SX50T FPGA with 8,160 slices and 288 DSP48 resources.<\/p>\n<h4>How Much DRAM Does It Provide?<\/h4>\n<p>It provides 512 MB divided into two independent 256 MB banks.<\/p>\n<h4>What Is the DRAM Bandwidth?<\/h4>\n<p>Each DRAM bank supports bandwidth up to approximately 1.6 GB\/s under supported conditions.<\/p>\n<h4>Does the PXIe-7962R Include Analog Inputs?<\/h4>\n<p>No fixed analog inputs are included on the FPGA carrier. Analog or digital I\/O is supplied by a compatible FlexRIO adapter module.<\/p>\n<h4>How Many Adapter Interface Lines Are Available?<\/h4>\n<p>The adapter interface provides 132 single-ended lines that can also operate as 66 differential LVDS pairs.<\/p>\n<h4>Does It Support Peer-to-Peer Streaming?<\/h4>\n<p>Yes. The PXIe-7962R can exchange data directly with compatible PXI Express instruments in a supported chassis configuration.<\/p>\n<h4>What Is the Maximum Streaming Rate?<\/h4>\n<p>The module can exceed 800 MB\/s in one direction. Simultaneous bidirectional operation can exceed 700 MB\/s per direction.<\/p>\n<h4>Which Software Is Required?<\/h4>\n<p>FPGA development normally requires compatible NI FlexRIO, LabVIEW and LabVIEW FPGA software, together with the appropriate Xilinx compilation tools.<\/p>\n<h4>Can a PXIe-7962R Bitfile Run on a PXIe-7976R?<\/h4>\n<p>No direct compatibility should be assumed. The PXIe-7976R uses a different FPGA architecture, so the project generally must be migrated and recompiled.<\/p>\n<h4>What Replaced the PXIe-7962R?<\/h4>\n<p>NI identified the PXIe-7976R as the replacement path, although FPGA code, adapter and software compatibility must be evaluated.<\/p>\n<h4>Is the PXIe-7962R Still Manufactured?<\/h4>\n<p>No. The PXIe-7962R is obsolete and availability is generally limited to surplus or previously installed equipment.<\/p>\n<h3>Request a Quote for the PXIe-7962R<\/h3>\n<p>Contact us for current availability, condition and project pricing for the <strong>PXIe-7962R Virtex-5 SX50T FlexRIO FPGA Module<\/strong>. We can also help verify the 781206-01 part number, adapter compatibility, software requirements and suitable PXIe-7976R migration options for your system.<\/p>","protected":false},"excerpt":{"rendered":"<p>PXIe-7962R Virtex-5 SX50T FlexRIO FPGA Module The PXIe-7962R, also listed as the PXIe-7962, is a PXI Express FlexRIO FPGA module<\/p>","protected":false},"featured_media":31837,"template":"","meta":{"_acf_changed":false},"product_brand":[18],"product_cat":[667],"product_tag":[],"class_list":["post-30585","product","type-product","status-publish","has-post-thumbnail","product_brand-national-instruments","product_cat-pxi-modules","first","instock","shipping-taxable","product-type-simple"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v25.0 (Yoast SEO v28.1) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>NI PXIe-7962 PXI FPGA Module for FlexRIO 781206-01, In Stock | Project Pricing<\/title>\n<meta name=\"description\" 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