{"id":29050,"date":"2025-09-16T14:23:30","date_gmt":"2025-09-16T06:23:30","guid":{"rendered":"https:\/\/pxisource.com\/?post_type=product&p=29050"},"modified":"2026-08-27T22:22:02","modified_gmt":"2026-08-27T14:22:02","slug":"pxie-6535","status":"publish","type":"product","link":"https:\/\/pxisource.com\/ru\/product\/pxie-6535\/","title":{"rendered":"PXIe-6535"},"content":{"rendered":"

PXIe-6535 32-Channel 10 MHz High-Speed Digital I\/O Module<\/h3>\n

\u0417\u0435\u043c\u043b\u044f NI PXIe-6535<\/strong> is a high-speed digital I\/O module designed for continuous data streaming, pattern generation, digital acquisition, change detection and custom protocol emulation. It provides 32 bidirectional single-ended digital channels<\/strong>, a maximum sample clock rate of 10 MHz<\/strong> and aggregate streaming bandwidth of up to 40 MB\/s<\/strong>.<\/p>\n

The module supports selectable 2.5 V, 3.3 V and 5 V TTL-compatible<\/strong> logic levels. Each channel offers independent direction control, allowing digital inputs and outputs to be combined within the same application.<\/p>\n

Its PXI Express interface supports continuous DMA transfer between the module and host memory. This makes the PXIe-6535 suitable for pattern I\/O, image and display device testing, protocol emulation and other applications requiring long or continuously changing digital data streams.<\/p>\n

PXIe-6535 Product Overview<\/h3>\n

The PXIe-6535 is the 10 MHz model in the NI PXIe-653x high-speed digital I\/O family. It provides the same 32-channel architecture and flexible timing functions as the higher-speed PXIe-6536 and PXIe-6537, but is optimized for applications that do not require more than 40 MB\/s of aggregate throughput.<\/p>\n

When all 32 channels are used, the module transfers a four-byte digital word with every sample clock. At the maximum 10 MHz sample rate, the resulting aggregate data throughput is 40 MB\/s.<\/p>\n

The PXIe-6535 supports hardware-timed pattern generation, continuous digital acquisition, handshake operation, change detection, pattern matching and software-timed static I\/O. Its standard NI part number is 780695-01<\/strong>.<\/p>\n

Key Features of the PXIe-6535<\/h3>\n

32 Bidirectional Digital Channels<\/h4>\n

The PXIe-6535 provides 32 single-ended digital I\/O channels. The channels can be used as one 32-bit interface or divided into smaller 8-bit, 16-bit and custom-width groups.<\/p>\n

Per-Channel Direction Control<\/h4>\n

Each digital line can be independently configured as an input or output. This provides greater flexibility than digital modules that require an entire port to operate in one direction.<\/p>\n

10 MHz Maximum Sample Clock<\/h4>\n

The module supports hardware-timed digital operations at sample clock rates up to 10 MHz. It can use its internal timing engine or an external clock supplied through a clock-capable PFI terminal or PXI backplane resource.<\/p>\n

Up to 40 MB\/s Aggregate Streaming<\/h4>\n

The PXIe-6535 can continuously stream 32-bit digital samples at up to 10 million samples per second, producing an aggregate transfer rate of 40 MB\/s.<\/p>\n

Actual sustained performance depends on the PXI Express chassis, controller, host memory, software buffers and other modules sharing the system bandwidth.<\/p>\n

Selectable Logic Levels<\/h4>\n

The PXIe-6535 supports 2.5 V, 3.3 V and 5 V TTL-compatible digital logic. The 5 V TTL-compatible mode uses 3.3 V output levels with input thresholds suitable for 5 V TTL signals.<\/p>\n

Continuous DMA Transfers<\/h4>\n

DMA transfers move generated and acquired data between the module and host memory. This architecture enables long-duration digital operations without requiring the complete waveform to fit within onboard memory.<\/p>\n

Pattern Generation and Acquisition<\/h4>\n

The module can generate predefined parallel patterns and acquire DUT responses using hardware sample-clock timing. These functions are useful for digital interface simulation and automated functional testing.<\/p>\n

Change Detection<\/h4>\n

Change-detection timing captures digital data when selected input channels transition. It reduces unnecessary data transfer in applications where the signals remain unchanged for long periods.<\/p>\n

Handshake Timing<\/h4>\n

Handshake and burst-handshake modes coordinate data transfers with external ready and acknowledge signals. These timing modes allow communication with devices that cannot sustain a continuous fixed-rate stream.<\/p>\n

PXI Clock and Trigger Routing<\/h4>\n

The PXIe-6535 can route timing signals through its PFI terminals and supported PXI Express backplane resources. It can therefore synchronize digital operations with other PXI \u043c\u043e\u0434\u0443\u043b\u0438<\/a>.<\/p>\n

PXIe-6535 Technical Specifications<\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Product Model<\/th>\nNI PXIe-6535<\/td>\n<\/tr>\n
Part Number<\/th>\n780695-01<\/td>\n<\/tr>\n
Product Type<\/th>\nHigh-Speed Digital I\/O Module<\/td>\n<\/tr>\n
Bus and Form Factor<\/th>\nPXI Express, single-slot 3U module<\/td>\n<\/tr>\n
Digital I\/O Channels<\/th>\n32 bidirectional channels<\/td>\n<\/tr>\n
Direction Control<\/th>\nPer channel<\/td>\n<\/tr>\n
Signaling Type<\/th>\nSingle-ended<\/td>\n<\/tr>\n
Maximum Sample Clock<\/th>\n10 MHz<\/td>\n<\/tr>\n
Maximum Per-Channel Data Rate<\/th>\n10 Mbit\/s<\/td>\n<\/tr>\n
Maximum Aggregate Streaming Rate<\/th>\n40 MB\/s with 32-bit data<\/td>\n<\/tr>\n
Supported Logic Families<\/th>\n2.5 V, 3.3 V and 5 V TTL compatible<\/td>\n<\/tr>\n
Digital Input Range<\/th>\n-1 V to 6 V<\/td>\n<\/tr>\n
Output Impedance<\/th>\n50 \u03a9 nominal<\/td>\n<\/tr>\n
Input Impedance<\/th>\n50 k\u03a9 nominal<\/td>\n<\/tr>\n
Maximum Drive Strength<\/th>\n\u00b116 mA at 2.5 V; \u00b132 mA at 3.3 V<\/td>\n<\/tr>\n
PFI Channels<\/th>\n6 bidirectional PFI channels<\/td>\n<\/tr>\n
Internal Timebase<\/th>\n200 \u041c\u0413\u0446<\/td>\n<\/tr>\n
Onboard FIFO<\/th>\n2,048 samples<\/td>\n<\/tr>\n
Transfer Methods<\/th>\nDMA and programmed I\/O<\/td>\n<\/tr>\n
Front Connector<\/th>\n1 \u00d7 VHDCI<\/td>\n<\/tr>\n
Driver<\/th>\n\u041d\u0418-DAQmx<\/td>\n<\/tr>\n
Module Width<\/th>\n1 PXI Express slot<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Understanding the 40 MB\/s Data Rate<\/h3>\n

The 40 MB\/s specification represents the aggregate transfer rate for all 32 digital channels. A 32-bit sample contains four bytes:<\/p>\n

10,000,000 samples\/s \u00d7 4 bytes\/sample = 40 MB\/s<\/strong><\/p>\n

Each individual channel therefore supports up to 10 Mbit\/s when the module operates at its maximum 10 MHz sample rate.<\/p>\n

This aggregate-bandwidth specification should not be confused with digital waveform instruments that normally specify data rate separately for each channel.<\/p>\n

How the PXIe-6535 Works<\/h3>\n

During digital generation, an application creates a host-memory buffer containing the required pattern data. NI-DAQmx transfers the data through the PXI Express bus to the module\u2019s onboard FIFO. The PXIe-6535 outputs each digital word according to the selected sample clock.<\/p>\n

During acquisition, the module samples the digital input channels and stores data temporarily in the FIFO. DMA continuously transfers the samples to host memory for storage, decoding or analysis.<\/p>\n

The FIFO helps absorb short variations in bus timing, while the PXI Express connection supplies the sustained bandwidth required for continuous operation.<\/p>\n

Supported Digital Timing Modes<\/h3>\n

Sample Clock Timing<\/h4>\n

Sample clock timing generates or acquires one digital word on every selected clock edge. The sample clock can come from the internal timing engine, a PFI terminal or a supported PXI backplane resource.<\/p>\n

Pipelined Sample Clock<\/h4>\n

Pipelined sample-clock timing provides additional timing control between the digital data and clock. It can help satisfy the setup-and-hold requirements of an external device.<\/p>\n

Burst Handshake<\/h4>\n

Burst-handshake timing transfers blocks of data while using external flow-control signals. This is useful when the DUT accepts or provides data in bursts rather than as a continuous stream.<\/p>\n

Handshake Timing<\/h4>\n

Handshake mode coordinates individual transfers with ready and acknowledge signals. It supports devices whose response time may vary between samples.<\/p>\n

Change Detection<\/h4>\n

Change-detection acquisition records digital states when selected channels change. Rising edges, falling edges or both edge directions can be monitored according to the application.<\/p>\n

On-Demand Digital I\/O<\/h4>\n

Software-timed operation is available for applications that do not require deterministic hardware timing. The host application can directly read or write digital states using NI-DAQmx.<\/p>\n

Continuous Digital Streaming<\/h3>\n

The PXIe-6535 is designed for continuous data movement rather than deep onboard waveform storage. Generated and acquired data can be transferred during operation, allowing tests to run for longer than the onboard FIFO capacity.<\/p>\n

Continuous streaming is useful for:<\/p>\n